Abstract
Cache coherence interconnects have recently emerged to integrate CPUs, accelerators, and memory components into a unified, heterogeneous computing domain. These interconnect technologies ensure data coherency between CPU memory and device-attached private memory, creating a new paradigm of globally shared memory and network space. Among several efforts to establish such connectivity, including Gen-Z [1] and Cache coherent interconnect for accelerators (CCIX) [2], Compute Express Link (CXL) has become the first open interconnect protocol capable of supporting diverse processors and device endpoints. With the absorption of Gen-Z, CXL stands out as a promising interconnect interface due to its highspeed coherence control and seamless compatibility with the widely adopted PCIe standard. This makes it particularly advantageous for a wide range of datacenter-scale hardware, including CPUs, GPUs, FPGAs, and domain-specific ASICs. Furthermore, the CXL consortium has highlighted its potential for memory disaggregation, enabling pooling of DRAM and byte-addressable persistent memory.
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