Choi, Jaehyouk Choi, Jaehyouk


Ph.D. (2010) Georgia Institute of Technology


  • “A 76fsRMS-jitter and –40dBc-integrated-phase-noise 28–31GHz frequency synthesizer based on digital sub-sampling PLL using optimally-spaced voltage comparators and background loop-gain optimization,” IEEE International Solid-State Circuits (ISSCC) 2019, February 2019.
  • “A 140fsRMS-jitter and −72dBc-reference-spur ring-VCO-based injection-locked clock multiplier using a background triple-point frequency/phase/slope calibrator,” IEEE International Solid-State Circuits (ISSCC) 2019, February 2019.
  • “A 0.5V-VIN, 0.29ps-Transient-FOM, and Sub-2mV-Accuracy Adaptive-Sampling Digital LDO Using Single-VCO-Based Edge-Racing Time Quantizer”, IEEE Symposium on VLSI Circuits 2019, June 2019.
  • “A -31dBc integrated-phase-noise 29GHz fractional-N frequency synthesizer supporting multiple frequency bands for backward-compatible 5G using a frequency doubler and injection-locked frequency multipliers,” IEEE International Solid-State Circuits (ISSCC) 2018, February 2018.
  • Self-sustaining water-motion sensor platform for continuous monitoring of frequency and amplitude dynamics,” Nano Energy (Elsevier) (IF = 12.343), May 2017.


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