Prof. Yang-Kyu Choi & Sung-Yool Choi’s research group were reported in Etnews about the wearable logic-in-memory using memristor on February 10th, 2018.
The research develops a wearable logic-in-memory based on memristors by weaving a special thread coated with electrode and polymer insulating layer.
The study was published in the October 2017 issue of the international journal "Nano Letters." (Impact factor 2017 : 12.080)
<Media> ‘KAIST, implementing storage and computation device by weaving the thread… Implementing new concept of the wearable device’
KAIST EE: ‘Research by Ph.D candidate Bae, Hak-Yeol and Jang, Byung-Cheol has been published in Nano Letters'
Article title: Functional Circuitry on Commercial Fabric via Textile-Compatible Nanoscale Film Coating Process for Fibertronics
A research article authored by Myung Hun Woo (KAIST EE), Byung Chul Jang (KAIST EE), Junhwan Choi (KAIST CBE), Khang June Lee (KAIST EE), Gwang Hyuk Shin (KAIST EE), Hyejeong Seong (KAIST CBE), Sung Gap Im (KAIST CBE), and Sung‐Yool Choi (KAIST EE; Corresponding author) was published at Advanced Functional Materials (2017.11)
Low-power, nonvolatile memory is an essential electronic component to store and process the unprecedented data flood arising from the oncoming Internet of Things era. Molybdenum disulfide (MoS2) is a 2D material that is increasingly regarded as a promising semiconductor material in electronic device applications because of its unique physical characteristics. However, dielectric formation of an ultrathin low-k tunneling on the dangling bond-free surface of MoS2 is a challenging task. Here, MoS2-based low-power nonvolatile charge storage memory devices are reported with a poly(1,3,5-trimethyl- 1,3,5-trivinyl cyclotrisiloxane) (pV3D3) tunneling dielectric layer formed via a solvent-free initiated chemical vapor deposition (iCVD) process. The surface-growing polymerization and low-temperature nature of the iCVD process enable the conformal growing of low-k (≈2.2) pV3D3 insulating films on MoS2. The fabricated memory devices exhibit a tunable memory window with high on/off ratio (≈106), excellent retention times of 105 s with an extrapolated time of possibly years, and an excellent cycling endurance of more than 103 cycles, which are much higher than those reported previously for MoS2-based memory devices. By leveraging the inherent flexibility of both MoS2 and polymer dielectric films, this research presents an important milestone in the development of low-power flexible nonvolatile memory devices.
Figure 1. A Schematic illustration of the fabricated memory device, which is composed of a pV3D3 tunneling dielectric, AuNPs as floating gate, and an Al2O3 blocking dielectric layer. B Cross-sectional TEM image of the device. C Initial transfer characteristics of the memory device with control gate voltage. The inset shows the memory device contact properties. D Transfer characteristics with VCG sweeping in the negative-to-positive direction and back, with fixed VDS = 1 V. E Extracted threshold voltage shift for different pulse widths, and calculated charge injection rate in program and erase operations.