Panmnesia, a faculty startup founded by Professor Myoungsoo Jung of the Department of Electrical Engineering, has proposed a next-generation AI datacenter architecture that makes an entire datacenter behave like a single chip, in collaboration with the global hyperscaler Meta. The invited review paper has been published in Nature Reviews Electrical Engineering (NREE), a journal published by Nature.
NREE review articles are written by invitation only: the journal directly commissions a small number of researchers and institutions that lead a given field. Nature’s decision to invite Panmnesia as the author for CXL and AI datacenter architecture reflects recognition of the company’s technology as representative of this field. Panmnesia became the first semiconductor startup in the world to lead an NREE review article, and this paper is also the first NREE review devoted to CXL technology and AI datacenter design. It is highly unusual for a university spin-off from Korea to be listed as a co-author alongside the datacenter infrastructure organization of a global big-tech company.
[Research Details]
As AI models grow rapidly, the scale of the hardware used to run a single AI is also expanding from an individual chip to the level of an entire datacenter. NVIDIA has unveiled the NVL72, which bundles a whole rack together, and AMD has likewise introduced its rack-scale AI system, “Helios.”
To build such enlarged systems, high-speed interconnect technologies such as NVLink and UALink have mainly been used. These have shown that tight coupling is possible, primarily within a single rack. However, because they are accelerator-centric connections, they cannot unify memory into a single resource as well, and it has been difficult to extend their scope across an entire datacenter.
The newly presented architecture is distinctive in that it places the CPU, accelerators, and memory into a single domain based on the open standard CXL (Compute Express Link), extending that scope across the whole datacenter. As a result, compared with a conventional network-based structure (a configuration connecting the GB200 NVL72 over Ethernet/InfiniBand), the number of accelerators tied together as one increases by about 13x, server-to-server round-trip access latency shortens from the microsecond range to the hundreds-of-nanoseconds range, and the unit of replacement upon failure shrinks from an entire server to a single component.
To achieve this, the team added dedicated hardware that eliminates latency variance—a high fan-out fabric switch, a Link Acceleration Unit (LAU), and a fabric controller—on top of CXL, and arranged these into a hierarchy of trays, pods, and fabrics following the same principle as a chip’s tile structure. Panmnesia has already implemented and validated these core components in silicon and is currently preparing for commercial supply.
[Closing Remarks]
Professor Jung leads the Computer Architecture and Memory/Storage Systems Laboratory (CAMELab) and has conducted long-term research on interconnect and memory/storage systems. In 2022, he founded Panmnesia, developing link solutions that make AI datacenters more efficient.
This achievement shows that research originating in our department has moved through a faculty startup to helping define the direction of next-generation AI infrastructure together with a global technology leader.
- Paper: One-chip-like datacenter design enabled by CXL-based scale-up fabrics
- Journal: Nature Reviews Electrical Engineering
- Link: https://www.nature.com/articles/s44287-026-00315-5
