Analog/Mixed-mode Integrated Circuit Design
LaboratoryMixed-Signal Integrated Circuits Lab.
- "An 8.6 ENOB 900MS/s Time-Interleaved 2b/cycle SAR ADC with a 1b/cycle Reconfiguration for Resolution Enhancement", ISSCC (2013)
- "A 6-b 4.1-GS/s Flash ADC with Time-Domain Latch Interpolation in 90-nm CMOS", JSSC (2013)
- "A Replica-Driving Technique for High Performance SC Circuits and Pipelined ADC Design", TCASII (2013)
- "Method and apparatus for digital error correction for binary successive approximation ADC", US Patent 7986253 (2009)
- "Method and apparatus digital error correction of successive approximation analog to digital converter", KOR Patent 2008-0107657 (2008)