Ph.D. (2002)Massachusetts Institute of Technology
- J. Lee, S. H. Cho, “A 1.4 W 24.9 ppm/ C current reference with process insensitive temperature compensation in 0.18 CMOS,” IEEE J. of Solid-State Circuits, Oct. 2012.
- D. Park, S. H. Cho, “A 14.2mW 2.55-to-3GHz cascaded PLL with reference injection and 800MHz modulator in 0.13 CMOS,” IEEE J. of Solid-State Circuits, Dec. 2012.
- J. Kim, W. Yu, S.H. Cho, “A digital-intensive receiver front-end using VCO-based ADC with an embedded 2nd-order antialiasing sinc filter in 90nm CMOS,” IEEE Int''l Solid-State Circuits Conf. (ISSCC), Feb. 2011.
- P. Park, H. Park, J. Park, S. H. Cho, “An all-digital clock generator using a fractionally injection-locked oscillator in 65nm CMOS,” IEEE Int''l Solid-State Circuits Conf. (ISSCC), Feb. 2012.
- K. S. Kim, Y. H. Kim, W. Yu, and S. H. Cho, “A 7b, 3.75ps resolution two-step time-to-digital converter in 65nm CMOS using pulse-train time amplifier,” Symp. on VLSI Circuits, 2012.