최성율 교수 연구팀, 뉴로모픽 칩에 적용 가능한 멤리스터 기반의 인공 시냅스 개발

우리 학부 최성율 교수님 연구팀에서 뉴로모픽 칩에 사용되는 멤리스터 기반의 인공 시냅스를 개발하여, 해당 소식이 국내 유수의 언론에 보도되었습니다. 생체 시냅스를 모방할 수 있는 멤리스터 기반의 인공 시냅스 제작 기술을 활용하여 연구팀은 뉴로모픽 칩의 구현 방안을 제안하였습니다.
장병철 박사(현재 삼성전자 연구원), 김성규 미국 노스웨스턴대 박사, 양상윤 KAIST 연구교수가 주도한 이번 연구는 나노 분야 국제학술지 ‘나노 레터스(Nano Letters)’ 에 2019년 2월 논문으로 게재되었습니다. (Impact factor 2018: 12.279)
(논문명: Polymer Analog Memristive Synapse with Atomic-Scale Conductive Filament for Flexible Neuromorphic Computing System)
자세한 보도 내용은 아래의 링크를 참조해주시기 바랍니다.

언론보도: ‘KAIST 연구진, 뉴로모픽 칩 시냅스 구현’ (동아사이언스 및 23개 언론사)
http://dongascience.donga.com/news/view/26734
KAIST News: ‘최성율 교수, 뉴로모픽 칩의 시냅스 구현’
https://www.kaist.ac.kr/_prog/_board/?mode=V&code=kaist_news&no=92321&si...

Article title: Polymer Analog Memristive Synapse with Atomic-Scale Conductive Filament for Flexible Neuromorphic Computing System

A research article authored by Byung Chul Jang (KAIST EE), Sungkyu Kim (Northwestern U), Sang Yoon Yang (KAIST EE), Jihun Park (KAIST EE), Jun-Hwe Cha (KAIST EE), Jungyeop Oh (KAIST EE), Junhwan Choi (KAIST CBE), Sung Gap Im (KAIST CBE), Vinayak P. Dravid (Northwestern U) and Sung-Yool Choi (KAIST EE; Corresponding author) was published in Nano Letters (2019.02)

The AI system leads to several issues such as limited computing power and high power consumption, making it very challenging to apply it to battery-powered mobile electronics with limited battery capacity. High power consumption of current computing hardware in the software-based implementation of artificial neural network (ANN) is mainly due to the von Neumann architecture, which is energy-inefficient for data-intensive tasks. To overcome these issues, hardware-based ANNs known as brain-inspired neuromorphic systems have been in the spotlight because the neuromorphic system can potentially emulate massively parallel networks of the biological brain with minimal energy consumption.

We demonstrate that flexible memristors with polymer switching layer called pV3D3 can be operated as an electronic synapse device featuring analog conductance updates simply by tuning the lateral size of the conducting filament. Reduction of the lateral size of the filament, that is, the formation of atomically thin Cu filament, resulted in the transition of switching behavior of pV3D3 memristors from abrupt to gradual mode. A linear potentiation-depression characteristic was obtained in this device, suggesting that conductance state can be updated effectively in an analog fashion when consecutive pulses are applied. Device-to-system level simulation of the face recognition also showed that the ANN based on pV3D3 memristors having atomically thin filament well classified the face images even when they were damaged.

Figure 1. A Schematic illustration of flexible pV3D3 memristor synapse array. B Analog switching behavior of polymer memristor. (Inset) Device structure of a memristor with the formation of atomically thin Cu filament. C Potentiation-depression characteristics of pV3D3 memristor. D Recognition rate of ANN for the face classification.

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