세미나

O Abstract:

A convolutional neural network (CNN) core inspired by the 3D NAND flash array was experimentally demonstrated in a standard 65nm CMOS process. Logic-compatible embedded flash memory cells were used for storing multilevel synaptic weights while a bit-serial architecture enables 8 bit x 8 bit multiply-and-accumulate operation. A novel back-pattern tolerant programverify scheme reduces the cell current variation to less than 0.6µA. Positive and negative weights are stored in adjacent bitlines, generating a differential output signal. Our eNAND based neural network core achieves a 98.5% handwritten digit recognition accuracy which is within 0.5% of the software accuracy for the same weight precision. To our knowledge, this work represents the first physical demonstration of an embedded NAND Flash based neuromorphic chip in a standard logic process.