As smart mobile and wearable devices are becoming more widely used, electrostatic discharge (ESD) is increasingly a major electromagnetic compatibility (EMC) problem and results in malfunctions of various electronic devices. It is important to pursue in-depth research on precise measurement and analysis of systemlevel ESD-induced soft failures. The coupling from ESD events can be effectively calculated using the partial element equivalent circuit (PEEC) method both in time and frequency domains. The PEEC method allows a fast and accurate calculation of system-level ESD noise coupling based on the model decomposition process, which separates small victim structures from the large aggressor structures. In addition to prediction of noises, statistical phenomena of the IC logic operation errors at a digital output are measured and analyzed. A simplified structure of a laptop PC and an IC are designed and tested. The input signals to the IC are accurately measured during the ESD tests, and validated with full-wave simulations. The statistical IC soft failures found from the SPICE simulations using the measured input signals are compared with the measured failures, and analyzed. Furthermore, the methods for reduction of ESD-induced IC soft failures are investigated.