Moore’s Law, doubling the number of transistors in a chip every two years, has so far been contributed to the evolution of computer system architectures, e.g., introducing manycore accelerations, employing large on-chip caches, and increasing DRAM (or main memory) capacity. The growth of such hardware implementation makes a lot of optimization opportunities available to software developers. Unfortunately, we cannot expect sustainable transistor shrinking anymore, i.e. the end of Moore’s Law will come. Although still device and manufacturing technologies have been progressing, some researchers predict that transistor shrinking may stop at around 2025 to 2030 due to physical or economic reasons. The goal of this research is to open the door for post-CMOS ultra high-performance, low-power computing. Our approach stands on device/circuit/architecture level co-designs by targeting an emerging device called SFQ (Single-Flux-Quantum). We have successfully demonstrated a physical design of about 48 GHz 5.6 mW (10 TOPS/W) 8bit Multiplier. This talk introduces the current status of our research for SFQ accelerator designs and discusses future directions of cryogenic computing platforms.