C. Shim, J. Bae, and B. Kim, “VIP-Sat: A Boolean Satisfiability Solver Featuring 5×12 Variable In-Memory Processing Elements with 98% Solvability for 50 Variables 218 Clauses 3-SAT Problems,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2024
J. Bae, W. Oh, J. Koo, and B. Kim, “CTLE-Ising: A 1,440 Spins Continuous-Time Latch-based Ising Machine with One-Shot Fully-Parallel Spin Updates Featuring Equalization of Spin States,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2023
C. Yu, T. Yoo, K. Chai, T. Kim, and B. Kim, “A 65nm 8T SRAM Compute-In-Memory Macro with Column ADCs for Processing Neural Networks,” IEEE Journal of Solid-State Circuits (JSSC), Nov. 2022
Y. Su, T. Kim, and B. Kim, “FlexSpin: A Scalable CMOS Ising Machine with 256 Flexible Spin Processing Elements for Solving Complex Combinatorial Optimization Problems,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2022
H. Kim, T. Yoo, T. Kim, and B. Kim, “Colonnade: A Reconfigurable SRAM-Based Digital Bit-Serial Compute-In-Memory Macro for Processing Neural Networks,” IEEE Journal of Solid-State Circuits (JSSC), Jul. 2021
J. Mu and B. Kim, “A 21×21 Dynamic-Precision Bit-Serial Computing Graph Accelerator for Solving Partial Differential Equations Using Finite Difference Method,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2021
Y. Su, H. Kim, and B. Kim, “CIM-Spin: A 0.5-1.2V Scalable Annealing Processor Using Digital Compute-In-Memory Spin Operators and Register-Based Spins for Combinatorial Optimization Problems,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2020
