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In the history of semiconductor, Moore’s law has been a guidance for the technology node transition for the industry. As the up-coming technology node’s dimension becomes sub-10nm, it has been reported that Moore’s law is approaching to its end. In this presentation, Ryoung-han Kim will discuss how Moore’s law is broken on the view of DTCO (Design Technology Co-Optimization), and how the industry is trying to progress the technology node with a slowdown in dimensional scaling. He will discuss how the traditional scaling has been performed with the metrics used, and show how the semiconductor industry is trying to change its paradigm in device, design and scaling in near term and long term.
Ryoung-han Kim is the group manager of OPC/RET, Imaging/Mask, and Test-site/Design Automation teams at IMEC. His scope covers the research and develop activities in design-technology co-optimization, computational lithography, mask solution and test sites support for advanced technology nodes across CMOS, beyond-CMOS and Photonics program in IMEC. Before joining IMEC, he was a Sr. Manager of lithography R&D at GLOBALFOUNDRIES, USA, where he was in charge of lithography of advanced technology nodes including 7nm and beyond with career at AMD and Texas Instruments. He received Ph.D. degree in Electrical engineering from Texas A&M University, College Station, TX with a focus on Integrated Optics, and B.S./M.S. from Yonsei University, Seoul, Korea.
Copyright ⓒ 2015 KAIST Electrical Engineering. All rights reserved. Made by PRESSCAT
Copyright ⓒ 2015 KAIST Electrical Engineering. All rights reserved. Made by PRESSCAT
Copyright ⓒ 2015 KAIST Electrical
Engineering. All rights reserved.
Made by PRESSCAT
