(December 1) Toward ultra-efficient computing on chip: multi-level approach and design examples

As CMOS technology has advanced considerably in the last few decades, various computing platforms have been implemented across different application areas due to reduced area and power consumption. But CMOS technology scaling started to slow down recently, which translates to the end of (somewhat) easy efficiency improvements. In addition, expanding application of recently introduced data processing algorithms such as deep learning is making the design issues even worse because of incomparably larger computational requirements.

Voltage scaling is one of the most promising power saving techniques due to quadratic switching power reduction effect, making it necessary feature for even high-end processors. However, deep voltage scaling incurs unavoidable performance degradation as well as enlarged variability, and hence must be accompanied by other efficiency and performance boosting techniques. In this talk, a systematic energy-aware design approach will be described. Considering prominent leakage and larger PVT variability in low operating voltages, multi-level energy saving techniques to be described are applied to key building blocks in energy-constrained applications: architecture study, algorithm-architecture co-optimization, and robust yet low-power memory design. Several design examples based on this approach including a face recognition accelerator demonstrate >10× power savings than state-of-the-art.