In-memory binary neural network accelerators have been garnering interests as an energy and area-efficient platform for lightweight applications. Most previous in-memory neural network accelerators, however, could not fully exploit the benefits of in-memory computing due to the high overhead of peripheral circuits such as analog-to-digital converters (ADCs). Such a problem becomes worse when a large scale neural network is mapped to the multiple memory arrays. In this talk, I will discuss the algorithm/hardware co-design techniques which my group has been working on to solve the issues. I will also introduce our SRAM-based in-memory Binary Neural Network (BNN) chip.