Abstract 

Energy Efficient Sensor interface

In the IoT era, a miniaturized sensor system serves as a key leaf node by collecting environment signals and bio-potentials. However, due to the small form factor and limited battery capacity, the energy efficiency of analog and mixed-signal circuits is a critical concern for the long-term operation of the sensor system. Especially, it poses a crucial challenge for the sensor interface circuits whose power consumption needs to be minimized while maintaining acquired signal accuracy and bandwidth. This short course discusses various sensor interface designs with improved noise and power efficiency.

Low Power Frequency Generation

Miniaturization and Interactive communication have been the two main topics dominating recent research in the internet-of-things. The high demand for continuous monitoring of environmental and bio-medical information has accelerated sensor technologies as well as circuit innovations. Simultaneously, the advances in communication methods and the widespread use of cellular and local data links enabled the networking of miniaturized sensor systems. In such systems, the reduction of sleep power is critical to make them sustainable with limited battery capacity or harvested energy. It makes the ultra-low-power wake-up timer a critical building block that must be designed with a stringent power budget. At the same time, precise frequency accuracy is also essential to maintaining synchronization for data communication. This short course will present fundamentals and recent innovations in ultra-low-power frequency reference circuits for miniaturized IoT systems. Two commonly adopted architectures, on-chip RC oscillators, and crystal oscillators, are introduced and discussed in terms of power consumption, noise, temperature sensitivity, line sensitivity, and calibration methods. Finally, a summary of the state-of-the-art designs and related challenges will be introduced.

Fully integrated DC-DC Conversion

Power management integrated circuits are essential building blocks of consumer electronics for the Internet of Things. Among various architectures, fully integrated power management circuits are promising candidates to provide small form factors and meet the high power density demand of modern computing platforms. However, several characteristics of on-chip passive components limit the performance of the fully integrated DC-DC converters, such as small inductance and Q-factor of the on-chip inductors and large parasitic bottom capacitance or low density of the on-chip capacitors. This short course will introduce the fundamentals of on-chip DC-DC converter designs as well as the latest designs with improved performance.

Low Noise Phase-Locked Loop

The generation of high-purity clock sources is becoming more crucial in today’s communication systems. With the advent of advanced communication systems such as 5G wireless radios and ultrahigh-speed wireline transceivers, the required clock jitter is now below 100 fs. However, it is hard to generate a clock with such a low jitter while satisfying other requirements, such as power and spur, due to conflicting trade-offs. This talk discusses various PLL topologies, such as charge-pump PLL, sub-sampling PLL, injection-locked PLL, bang-bang PLL, and reference oversampling PLL. Also, it introduces widely adopted circuit techniques and the latest designs.