[보관함:] AI in Wave division

우리 학부 이준구 교수님 연구팀이 독일 및 남아공 연구팀과의 협력 연구를 통해 비선 형 양자 기계학습 인공지능 알고리즘을 개발하였습니다.

이번 연구를 통해 비선형 커널이 고안되어 복잡한 데이터에 대한 양자 기계학습이 가능하게 되었습니다. 특히 이준구 교수님 연구팀이 개발한 양자 지도학습 알고리즘은 학습에 있어 매우 적은 계산량으로 연산이 가능하여, 대규모 계산량이 필요한 현재의 인공지능 기술을 추월할 가능성을 제시한 것으로 평가를 받고 있습니다.

이준구 교수님 연구팀은 학습데이터와 테스트데이터를 양자 정보로 생성한 후 양자 정보의 병렬연산을 가능하게 하는 양자포킹 기술과 간단한 양자 측정기술을 조합해 양자 데이터 간의 유사성을 효율적으로 계산하는 비선형 커널 기반의 지도학습을 구현하는 양자 알고리즘 체계를 만들었습니다. 이후 IBM 클라우드 서비스를 통해 실제 양자컴퓨터에서 양자 지도학습을 실제 시연하는 데 성공했습니다. KAIST 박경덕 연구교수가 공동 제1 저자로 참여한 이번 연구결과는 국제 학술지 네이처 자매지인 `npj Quantum Information’ 誌 2020년 5월 6권에 게재되었습니다. (논문명: Quantum classifier with tailored quantum kernel).

연구팀은 이와 함께 양자 회로의 체계적 설계를 통해 다양한 양자 커널 구현이 가능함을 이론적으로 증명했습니다. 커널 기반 기계학습에서는 주어진 입력 데이터에 따라 최적 커널이 달라질 수 있으므로, 다양한 양자 커널을 효율적으로 구현할 수 있게 된 점은 양자 커널 기반 기계학습의 실제 응용에 있어 매우 중요한 성과입니다.

이 연구에 참여한 박경덕 연구교수님은 “연구팀이 개발한 커널 기반 양자 기계학습 알고리즘은 수년 안에 상용화될 것으로 예측되는 수백 큐비트의 NISQ(Noisy Intermediate-Scale Quantum) 컴퓨팅의 시대가 되면 기존의 고전 커널 기반 지도학습을 뛰어넘을 것ˮ이라면서 “복잡한 비선형 데이터의 패턴 인식 등을 위한 양자 기계학습 알고리즘으로 활발히 사용될 것ˮ이라고 말했습니다.

한편 이번 연구는 각각 한국연구재단의 창의 도전 연구기반 지원 사업과 한국연구재단의 한-아프리카 협력기반 조성 사업, 정보통신기획평가원의 정보통신기술인력 양성사업(ITRC)의 지원을 받아 수행되었습니다.

아래의 링크에서 관련 논문에 대한 정보를 확인하실 수 있습니다.

다시 한 번, 양자 분야에서 뛰어난 행보를 보이시는 이준구 교수님 연구팀 성과에 박수를 보냅니다.

[Link]

https://www.nature.com/articles/s41534-020-0272-6

Title: Quantum tomography via classical machine learning

Authors: Changjun Kim, Daniel Kyungdeock Park, June-Koo Kevin Rhee

Determination of a wave function or a density matrix of a quantum system and/or its dynamics is of fundamental importance in quantum information science. Unfortunately, the computational cost of full quantum state and process tomography grow exponentially with the number of qubits. In this research project, we are exploring the possibilities to apply classical machine learning techniques such as linear regression and deep learning to assist quantum tomography tasks.

Signal Integrity/Power Integrity Design for AI Computing Hardware

1. Signal Integrity/Power Integrity Design of Energy-efficient Processing-in-memory in High Bandwidth Memory (PIM-HBM) Architecture to Accelerate AI Applications

Fig. 1. Conceptual view of heterogeneous PIM-HBM architecture

As the demand on high computing performance for artificial intelligence is increasing, parallel processing accelerators are the key factor of system performance. The important feature of these accelerator is high DRAM bandwidth required. That mean DRAM access occurs more frequently. In addition, the energy of DRAM access is about 200 times one 32bit floating-point operation and this gap increases with transistor scaling. In aspect of accelerator, the number of cores is continuously increasing, which requires more off-chip memory bandwidth and area. As a result, it not only increases the energy consumed by interconnection, but also limits system performance by insufficient off-chip memory bandwidth. In order to overcome the limitation, Processing-In-Memory (PIM) architecture is re-emerged. PIM architecture is the integration of processing units with memory, which can be implemented by 3D-stack high bandwidth memory (HBM).

Our lab’s AI hardware group focused on the optimized design of PIM-HBM architecture and interconnection considering signal integrity (SI) / power integrity (PI). In order to provide high memory bandwidth to the PIM core using through silicon via (TSV), area or data rates of TSV should be increased. However, more than 30% of DRAM area is already occupied by TSV, and data rates of TSV is determined by SI. Therefore, optimal design of TSV should be essential for small area and high bandwidth. Also, when the number of PIM cores increases for high performance, more area of logic die is required. That mean memory bandwidth for host processor is decreased by increased interposer channel length. Consequently, design of PIM-HBM logic die and interposer channel must be optimized for system performance without degradation of interposer bandwidth. Through system level optimization as mentioned above, our PIM-HBM architecture can achieve high energy-efficiency by drastically reducing interconnection lengths and improve system performance in memory-limited applications.

2. Signal Integrity/Power Integrity in a Memristor Crossbar Array for Neural Network Accelerator and Neuromorphic Chip

The most important part of artificial intelligence calculations is huge parallel matrix-vector multiplication. Such an operation method is inefficient in terms of calculation time and power in the conventional Von-Neumann computing architecture. This is because the data for the operation must be fetched from off-chip memory, which consumes lots of interconnection power, every clock cycle. Various AI hardware operation architectures are emerging to solve this problem. Among them, the promising structure is to integrate computation into the memory using non-volatile resistive memory. This architecture can reduce the access to off-chip memory for data fetch and calculate vector-matrix multiplication directly by reading current from the multiplication of voltage and conductance of memory as an analog computing approach. Thus, calculation for AI can be done very efficiently based on hardware structure target.

Our lab’s AI hardware group focused on the design of optimized computing architecture and interconnection considering signal integrity (SI) / power integrity (PI) for accurate hardware operation. Generally, memristor crossbar array has smaller size than the number of input neurons in a filter layer. But large-scale memristor crossbar array has serious IR drop problem, and can be more sensitive to noise such as crosstalk and ripple at high speed. In particular, it is more serious in a multi-level input calculation because of small voltage margin. We analyze SI/PI issues such as crosstalk noise between crossbar interconnection and power/ground noise that can affect to memristor resistance change and calculation. These noise can cause a large malfunction in the calculation of the small read voltage margin. Finally, we suggest design guide of memristor crossbar array for hardware AI operation.

Fig. 2. Signal Integrity/Power Integrity in a Memristor Crossbar Array for Hardware-based Matrix-Vector Multiplication

Professor Joungho Kim writes weekly column articles, “Kim Joungho Column on Strategies in the AI Era,” in the Opinion Section of Chosum.com. In his column series, he discloses various aspects of AI technologies in the IT industries from his insightful technical analysis and visionary insights on the future development of AI applications.

link : http://news.chosun.com/site/data/html_dir/2019/06/16/2019061602215.html

Title: ​Quantum-classical reinforcement learning for quantum algorithms with classical data

Authors: Daniel Kyungdeock Park, Jonghun Park, June-Koo Kevin Rhee

Many known quantum algorithms with quantum speed-ups require an existence of a quantum oracle that encodes multiple answers as quantum superposition. These algorithms are useful for demonstrating the power of harnessing quantum mechanical properties for information processing tasks. Nonetheless, these quantum oracles usually do not exist naturally, and one is more likely to work with classical data. In this realistic scenario, whether the quantum advantage can be retained is an interesting and critical open problem.

In our research group, we tackle this problem with the learning parity with noise (LPN) algorithm as an example. LPN is an example of an intelligent behavior that aims to form a general concept from noisy data. This problem is thought to be classically intractable. The LPN problem is equivalent to decoding a random linear code in the presence of noise, and several cryptographic applications have been suggested based on the hardness of this problem and its generalizations. However, the ability to query a quantum oracle allows for an efficient solution. The quantum LPN algorithm also serves as an intriguing counterexample to the traditional belief that a quantum algorithm is more susceptible to noise than classical methods. However, as noted above, in practice, a learner receives data from classical oracles. In our work, we showed that a naive application of the quantum LPN algorithm to classical data that is encoded as an equal superposition state requires an exponential sample complexity, thereby nullifying the quantum advantage.

We developed a quantum-classical hybrid algorithm for solving the LPN problem with classical examples. The underlying idea of our algorithm is to learn the quantum oracle via reinforcement learning, for which the reward is determined by comparing the output of the guessed quantum oracle and the true data, and the action is chosen via greedy algorithm. The reinforcement learning significantly reduces both the sample and the time cost of the quantum LPN algorithm in the absence of the quantum oracle. Simulations with a hidden bit string of length up to 12 show that the quantum-classical reinforcement learning performs better than known classical algorithms when the number of examples, run time, and robustness to noise are collectively considered.

링크 : http://meetings.aps.org/Meeting/MAR19/Session/K27.9

The recent study on artificial neural network signal equalization authored by Ahmed Galib Reza (KAIST EE) and June-Koo Kevin Rhee has been published in IEEE Photonics Technology Letters.  ( https://ieeexplore.ieee.org/document/8401897 )

Article Content:

Title: Nonlinear Equalizer Based on Neural Networks for PAM-4 Signal Transmission Using DML

Authors: Ahmed Galib Reza, and June-Koo Kevin Rhee

Nonlinear distortion from a directly modulated laser (DML) is one of the major limiting factors to enhance the transmission capacity beyond 10 Gb/s for an intensity modulation direct-detection optical access network. In this letter, we propose and demonstrate a low-complexity nonlinear equalizer (NLE) based on a machine-learning algorithm called artificial neural network (ANN). Experimental results for a DML-based 20-Gb/s signal transmission over an 18-km SMF-28e fiber at 1310-nm employing pulse amplitude modulation (PAM)-4 confirm that the proposed ANN-NLE equalizer can increase the channel capacity and significantly reduce the impact of nonlinear penalties.