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A structured packet-switched Networks-on-Chip (NoC) is designed and implemented for high-performance heterogeneous SoC design platform.
The chip integrates multiprocessors, multiple memories, and other heterogeneous Intellectual Properties and interconnection with 51mW and 1.6GHz on-chip networks.
The NoC adopts a partial activated crossbar, low-energy coding, and low-swing signaling for the power consumption optimization.
A Network-in-Package integrating four NoCs is fabricated in a 676-BGA-type package for larger and scalable systems and demonstrates 2D-image-processing and 3D-graphics applications.
