|▲ Lee, Hyunjin|
Symposium on VLSI Technology, Best Student Paper Award
Hyunjin Lee who is studying for Ph. D degree at the NanO-Bio-Electronic-Laboratory in KAIST received the Best Student Paper Award in the Symposium on VLSI Technology held at Kyoto, Japan on June 13th.
It is the first time that a graduate student in Korea wins the prize with the research result worked on in Korea.
Last year, she also won the same prize at the same symposium with the thesis, Sub-5nm All-Around Gate FinFET for Ultimate Scaling. This paper has been valued that it made a great step through the limitation of silicon semiconductor technology by suggesting the new structure and the skill of the Tera-scale semiconductor devices.
The Best Student Paper Award is selected as the most effective thesis in VLSI technology by both IEEE(The IEEE Electron Devices Society) and AP (The Japan Society of Applied Physics).
The Symposium on VLSI Technology, 27th this year, is the biggest level of world international semiconductor symposium which is held every year either in Kyoto, Japan or in Hawaii, USA.
○ Thesis: “Sub-5nm All-Around Gate FinFET for Ultimate Scaling”
by H. Lee, L.-E. Yu, S.-W. Ryu, J.-W. Han, K. Jeon, D.-Y. Jang, K.-H. Kim, J. Lee, J.-H. Kim, S. C. Jeon, G. S. Lee, J. S. Oh, Y. C. Park, W. H. Bae, H. M. Lee, J. M. Yang, J. J. Yoo, S. I. Kim and Y.-K. Choi
Sub-5nm all-around gate FinFETs with 3nm fin width were fabricated for the first time. The n-channel FinFET of sub-5nm with 1.4nm HfO2 shows an IDsat of 497 A/ m at VG=VD=1.0V. Characteristics of sub-5nm transistor are verified by using 3-D simulations as well as analytical models. A threshold voltage increases as the fin width reduces by quantum confinement effects. The threshold voltage shift was fitted to a theoretical model with consideration of the first-order perturbation theory. And a channel orientation effect, based on a current-flow direction, is shown.