Shin, Youngsoo

Shin, Youngsoo

Research Group

Circuit

division

Research Areas

AI & Machine Learning, Integrated Circuits & Semiconductor Systems, Semiconductor Devices & Nanotechnology

Research

Design Technology for VLSI and PIM, Computational Lithography

Laboratory

Semiconductor Design Technology Lab.

Building

School of Electrical Engineering (E3-2)

6206

Extension

#3479

Email

youngsoo-p@kaist.ac.kr

Website

http://dtlab.kaist.ac.kr/

Degree

Ph.D. (2000) Seoul National Univ.

Achievements

“Pulse width allocation and clock skew scheduling: optimizing sequential circuits based on pulsed latches,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 29, no. 3, pp. 355-366, Mar. 2010.
“Power gating: circuits, design methodologies, and best practice for standard-cell VLSI designs,” ACM Transactions on Design Automation of Electronic Systems, vol. 15, no. 4, article 28, pp. 28:1-28:37, Sep. 2010.
“Retiming pulsed-latch circuits with regulating pulse width,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 30, no. 8, pp. 1114-1127, Aug. 2011.
“Synthesis of active-mode power-gating circuits,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 31, no. 3, pp. 391-403, Mar. 2012.
“Clock gating synthesis of pulsed-latch circuits,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 31, no. 7, pp. 1019-1030, July 2012.