교수

교수

교수

신영수

Shin, Youngsoo
신영수.jpg

연구디비젼

Circuit

주요 연구

VLSI Design Technology, Low-Power, Statistical Design, Logic Synthesis

소속연구실

초고집적회로 설계 기술 연구실

위치

나노종합기술원 (E19)

, 204

연락처

3479

학위
Ph.D. (2000) Seoul National Univ.
대표업적
  • “Pulse width allocation and clock skew scheduling: optimizing sequential circuits based on pulsed latches,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 29, no. 3, pp. 355-366, Mar. 2010.
  • “Power gating: circuits, design methodologies, and best practice for standard-cell VLSI designs,” ACM Transactions on Design Automation of Electronic Systems, vol. 15, no. 4, article 28, pp. 28:1-28:37, Sep. 2010.
  • “Retiming pulsed-latch circuits with regulating pulse width,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 30, no. 8, pp. 1114-1127, Aug. 2011.
  • “Synthesis of active-mode power-gating circuits,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 31, no. 3, pp. 391-403, Mar. 2012.
  • “Clock gating synthesis of pulsed-latch circuits,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 31, no. 7, pp. 1019-1030, July 2012.

Copyright ⓒ 2015 KAIST Electrical Engineering. All rights reserved. Made by PRESSCAT

Copyright ⓒ 2015 KAIST Electrical Engineering. All rights reserved. Made by PRESSCAT

34141 대전광역시 유성구 대학로 291
한국과학기술원(KAIST)
Tel. 042-350-3411   Fax. 042-350-3410

Copyright ⓒ 2015 KAIST Electrical
Engineering. All rights reserved.
Made by PRESSCAT