Dr. Taein Shin from Professor Jeongho Kim’s research lab has been selected as a recipient of the ‘Best Paper Award’ at ‘DesignCon 2025,’ a prestigious international conference in semiconductor design.
Dr. Shin had previously won the same award at ‘DesignCon 2022’ three years ago. At that time, Professor Jeongho Kim’s research lab (KAIST TERA Lab) gained significant attention from industry and academia as four of its students, including Dr. Shin, Seongguk Kim, Seonguk Choi, and Hyeyeon Kim, were honored with the Best Paper Award, which was given to only eight recipients among all submitted papers.
‘DesignCon’ is a globally recognized international conference in semiconductor and package design. Each year, researchers and engineers from leading global tech companies such as Intel, NVIDIA, Google, Micron, Rambus, Texas Instruments (TI), AMD, IBM, and ANSYS, as well as students from renowned universities worldwide, participate in this conference held in Silicon Valley, USA.
‘DesignCon’ calls for paper abstracts at the end of June each year and conducts a rigorous review process until the end of December. The submitted papers predominantly focus on practical technologies closely related to industry applications or those that can be directly implemented in products.
Among all submitted papers, only up to 20 are shortlisted as Best Paper Award nominees. The authors of these nominated papers must attend the conference in person and deliver a 45-minute oral presentation, after which a strict evaluation process determines the final eight recipients of the Best Paper Award.
Dr. Shin attended the ‘DesignCon 2025’ international conference, which was held in San Jose, Silicon Valley, from January 28 for three days. He presented his research alongside fellow KAIST TERA Lab members—Hyeyeon Kim, a Ph.D. student, and Hyunjun Ahn, an M.S. student—who were also nominated for the Best Paper Award.
A TERA Lab representative stated, “Dr. Shin’s paper was selected from over 100 papers accepted by the conference in late 2024. His contribution to technological innovation in the field was highly regarded by the judging panel.”
Dr. Shin’s paper, titled “PSIJ-Based Integrated Power Integrity Design for HBM Using Reinforcement Learning: Beyond the Target Impedance,” introduces a methodology that optimizes power integrity design for high-bandwidth memory (HBM) packages. His approach utilizes power supply noise-induced jitter (PSIJ) as a criterion, incorporating AI to optimize design parameters affecting jitter, drawing significant attention from the academic and industrial communities.
The TERA Lab representative further emphasized, “Dr. Shin’s research received high praise from the judges for overcoming the limitations of traditional impedance-based power delivery network (PDN) design by leveraging reinforcement learning and power supply noise jitter. The originality of applying AI to this field was also highly rated.”
Dr. Shin stated, “As next-generation HBM-based package systems continue to advance in speed to support large-scale AI implementations, I aim to establish a foundation for semiconductor signal and power integrity design based on the proposed methodology.”
Meanwhile, as of March 2025, Professor Jeongho Kim’s research lab comprises 27 students, including 17 master’s and 10 Ph.D. candidates. The lab is conducting research on optimizing various semiconductor package and interconnection designs in both front-end and back-end processes using AI and machine learning techniques such as reinforcement and imitation learning. Additionally, the lab is actively researching HBM-based computing architectures for large-scale AI implementations.
