Professor Seungwon Shin’s Research Team Publishes Paper at Top Conference in Computer Science (USENIX Security)
<Professor Seungwon Shin>
Our department’s professor Seungwon Shin’s research team has announced findings that the data prefetching feature in Apple’s new M-series processors can be more effectively exploited for traditional cache attacks. Data prefetching is one of the key optimization functions of a processor, used to reduce memory access time by preloading data into the cache that the program is expected to need.
Processors typically provide hardware-based prefetching along with a set of instructions to support software-based prefetching. Professor Seungwon Shin’s team conducted a comparative analysis of the Instruction Set Architectures (ISA) of x86 and ARM, proving that the data prefetching feature on ARM-based processors can be more effectively utilized for cache attacks.
Through this research, they devised three new cache-based attacks and demonstrated that a covert channel implemented on Apple’s M-series processors could transmit data at over three times the speed of traditional cache attacks. Additionally, they proved approximately 8 times performance improvement in side-channel attacks that extract encryption keys compared to previous works.
Professor Seungwon Shin’s team emphasized the significance of starting the research on security vulnerabilities in ARM-based processors, especially as Apple has started to manufacture desktop processors based on ARM architecture.
This study will be presented at USENIX Security, one of the top conferences in computer security, in August 2024 and can be found on the conference’s website.
