(Apr 16) Heterogeneous Integration toward Monolithic 3D Chip

Monolithic 3D (M3D) integration has emerged as a promising technological solution for traditional transistor scaling limitations and interconnection bottleneck. It allows the reduction of the interconnect delay, resulting in reduction of the power consumption of the chip, not only the area reduction. Moreover, with M3D, many other components such as digital, analog, sensors, display, etc. can be heterogeneously integrated together in a single chip, which can provide enhanced functionality. Heterogeneous integration of different materials combined with M3D is more powerful, because it gives us more process design flexibility, which cannot be obtained in 2D integration (ex. common gate stack process for n-/p-FETs). Furthermore, it naturally has many benefits from their superior physical properties such as high mobility, direct bandgap, etc. Now, the challenge we must overcome is a processing temperature limit for top side devices in order to maitain proper performance of bottom side devices. To solve this problem, we developed a low temperature FET process for III-V materials and low temperature III-V and Ge layer stacking process using wafer bonding and epitaxial lift-off, since these materials can be processed at a low temperature and provide extended opportunity/functionality via heterogeneous integration. In this talk, I will try to give the brief introduction about the field of M3D and my research activity on low temperature process device fabrication and material stacking of III-V and Ge. Finally, I will talk about its applicability to mid-infrared photonics platform, thin film photodiodes, and MicroLED display for creating the ultimate multi-functional 3D chip of the future.