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(Jun 7) Design and Automatic Generation of High-Speed Analog and Mixed-Signal Circuits


Design and Automatic Generation of High-Speed Analog and Mixed-Signal Circuits


2018.06.07 (Thu) 16:00-


Dr. Jaeduk Han (Univ. of California at Berkeley)


Wooribyul Seminar Room (B/D E3-2 , #2201 )


The continual advances in electronic systems have enhanced the performance of integrated circuits, increasing demands on high-bandwidth analog and mixed-signal (AMS) circuits and systems for data acquisition and transfer. In contrast to the rapid increase in bandwidth that will be necessary, the allowable power consumption of the high-speed AMS circuits remains relatively constant. For example, next-generation high-speed wireline transceivers are required to achieve 50-60Gb/s, with 3-5pJ/bit energy efficiency to remain within the current total power window, which is a very challenging task to achieve within a reasonable amount of design time and budget. In this talk, various techniques in different levels are investigated extensively to address the challenges in performance, power consumption, and design efficiency. Circuit level innovations, such as current integration combined with cascode gate-voltage bias and resonant clocking are introduced to achieve the high operating frequency with low power consumption. These improvements are then combined with proper system design techniques to relax the overall requirements. Examples are interleaved samplers, per-path signaling path conditioning, and baud-rate clock recovery. Finally, to enhance the productivity and quality of the AMS design, the design flow is automated using the generator-based design methodology, to produce the final sized schematic and LVS clean layout rapidly, with optimal performance and power consumption for the target technology. 

 Three design examples utilizing the aforementioned techniques are introduced with measurement results: 1) A 60Gb/s receiver frontend with full equalization capability in 65nm CMOS process, 2) A 60Gb/s serial-link transceiver with equalizer adaptation and baud-rate clock recovery in 65nm, and 3) A time-interleaved SAR ADC entirely generated from the automated flow in 16nm FINFET. Their outstanding performances demonstrate the benefit of the proposed approaches.


Jaeduk Han (S’15) received the B.S. and M.S. degrees in electrical engineering from Seoul National University, Seoul, South Korea, in 2007, and 2009, respectively and Ph.D. degree in electrical engineering with the University of California, Berkeley, CA, USA in 2017. He was a Circuit Design Engineer with TLI, Seongnam, South Korea, from 2009 to 2012. He has held various engineering intern positions at Altera, San Jose, CA, USA, Intel, Hillsboro, OR, USA, Xilinx, San Jose, and Apple, Cupertino, CA, USA, in 2012, 2014, 2015, and 2016, respectively, where he was involved in high-speed wireline communication circuits and power management circuits. His current research interests include high-speed wireline communication circuit design and analog circuit design automation.