News & Event


News & Event


(Jun 26) Area- and Energy-Efficient Neural Recording Architecture for Advanced Neuroscience Research Tool


Area- and Energy-Efficient Neural Recording Architecture for Advanced Neuroscience Research Tool


2018.06.26 (Tue) 11:00-


Dr. Sung-Yun Park (University of Michigan)


Wooribyul Seminar Room (B/D E3-2 , #2201 )


Over the past years, neural recording interface have significantly progressed to provide high-quality, parallel recordings of neural activities at low power in a small form factor, while dramatically increasing the number of channels. According to a recent survey, the number of parallel recording channels has steadily increased since the initial demonstration of the unit recording in 1960, doubling every seven years similar to Moore’s law, although in much slower pace. While various neural interface systems such as neural prosthetics and Brain-Computer Interface can take the advantage of such rapid growth of the technologies, it is particularly beneficial to the comprehensive neuroscience research since high quality and parallel monitoring over a large number of neurons within small volume of brain can solely provide in-depth understanding of brain’s structure and activities. 

This talk mainly focuses on the development of system architectures and associated electronic circuits for a next generation neuroscience research tool, i.e. a massive-parallel neural recording system capable of recording 1,024 channels simultaneously. Three interdependent prototypes have been recently developed to address major challenges in realization of the massive-parallel neural recording microsystems: minimization of energy and area consumption while preserving high quality in electrical recordings. First, a modular 128-channel Δ-ΔΣ analog front-end (AFE) using the spectrum shaping technique has been designed and realized in silicon to propose an area-and energy efficient solution for neural recording AFEs. The fabricated AFE is also expandable to a 1,024-channel parallel recording system via hybrid assembly with the customized 3-dimension platform. Second, an on-chip mixed signal neural signal compressor has been built to reduce the energy consumption in handling and transmission of the recorded data since this occupies a large portion of the total energy consumption as the number of parallel recording increases. The compressor reduces the data rates of two distinct groups of neural signals that are essential for neuroscience research: local field potentials (LFP) and action potentials (AP) without loss of informative signals. Third, for the completeness of the system, a compact on-chip dc-to-dc converter with constant switching frequency has been developed to provide reliable power supplies and enhance energy delivery efficiency to the massive-parallel neural recording systems.

Finally, the last part of this talk briefly deals with the recent efforts to achieve the highest density in neural recording, which enables the integration of >1,000 channel in a small die (5 × 2.5 mm2) for a true massive-parallel neural recording by the combination of a MEMS-based assembly technique and integrated circuit design techniques.


Sung-Yun Park received his B.S. in Electrical Engineering from Pusan National University, Busan, Korea in 2005, and his M.S. in Electrical Engineering from Korean Advanced Institute of Science and Technology, Daejeon, Korea in 2008, where he was involved in photonic device research. From 2008 to 2010, he worked for the Fairchild Semiconductor, Bucheon, Korea, as a high voltage mixed-signal integrated circuit designer. He continued his study in integrated circuits in Cornell University, Ithaca, NY and received the M. Eng. in Electrical and Computer Engineering in 2011, and his Ph.D. in Electrical Engineering at the University of Michigan in 2016. From 2016 to 2018, he was a postdoctoral research fellow in the University of Michigan, and he is currently an assistant research scientist in the same place. His current research interests are in low power, low noise mixed-signal integrated circuits and power management circuits for biomedical applications.