Moore’s Law has been the driving force behind the exponential growth in the semiconductor industry for the past five decades. Today, energy efficiency and reliability challenges in nanoscale CMOS (and beyond CMOS) processes threaten the continuation of Moore’s Law. This talk will describe our work on developing a Shannon-inspired statistical information processing framework that seeks to address this issue by treating the problem of computing on unreliable devices and circuits as one of information transfer over an unreliable/noisy channel. Such a paradigm seeks to transform computing from its von Neumann roots in data processing to Shannon-inspired information processing. Key elements of this paradigm are the use of statistical signal processing, machine learning principles, equalization and error-control, for designing error-resilient on-chip computation, communication, storage, and mixed-signal analog front-ends. The talk will provide a historical perspective and demonstrate examples of Shannon-inspired designs of on-chip subsystems. The talk will conclude with a brief overview of the Systems On Nanoscale Information fabriCs (SONIC) Center, a multi-university research center focused on developing a Shannon/brain-inspired foundation for information processing on CMOS and beyond CMOS nanoscale fabrics. SONIC is funded by the US Department of Defense and the Semiconductor Research Corporation, and is a collaboration between the University of Illinois at Urbana-Champaign (lead), University of California at Berkeley, Stanford University, University of California at San Diego, University of California at Santa Barbara, University of Michigan at Ann-Arbor, Princeton University and Carnegie Mellon University.
Naresh R. Shanbhag is the Jack Kilby Professor of Electrical and Computer Engineering in the Department of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign. His research interests are in the design of robust and energy-efficient integrated circuits and systems for communications including VLSI architectures for error-control coding, and equalization, noise-tolerant integrated circuit design, error-resilient architectures and systems, and system-assisted mixed-signal design. Dr. Shanbhag received the 2010 Richard Newton GSRC Industrial Impact Award, became an IEEE Fellow in 2006, received the 2006 IEEE Journal of Solid-State Circuits Best Paper Award, the 2001 IEEE Transactions on VLSI Best Paper Award, the 1999 IEEE Leon K. Kirchmayer Best Paper Award, the 1999 Xerox Faculty Award, the Distinguished Lecturership from the IEEE Circuits and Systems Society in 1997, the National Science Foundation CAREER Award in 1996, and the 1994 Darlington Best Paper Award from the IEEE Circuits and Systems Society. Dr. Shanbhag is serving as an Associate Editor for the IEEE Journal on Exploratory Solid-State Computation Devices and Circuits (2014-16), served as an Associate Editor for the IEEE Transaction on Circuits and Systems: Part II (97-99) and the IEEE Transactions on VLSI (99-02 and 09-11), respectively. He was the General Chair of the 2013 IEEE Workshop on Signal Processing Systems, the General co-Chair of the 2012 IEEE International Symposium on Low-Power Design (ISLPED), the Technical Program co-Chair of the 2010 ISLPED, and served on the technical program (wireline subcommittee) committee of the International Solid-State Circuits Conference (ISSCC) from 2007-11. Since January 2013, he is the founding Director of the Systems On Nanoscale Information fabriCs (SONIC) Center, a 5-year multi-university center funded by DARPA and SRC under the STARnet phase of FCRP. In 2000, Dr. Shanbhag co-founded and served as the Chief Technology Officer of Intersymbol Communications, Inc., a venture-funded fabless semiconductor start-up that provides DSP-enhanced mixed-signal ICs for electronic dispersion compensation of OC-192 optical links. In 2007, Intersymbol Communications, Inc., was acquired by Finisar Corporation, Inc.