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신영수

Shin, Youngsoo

연구디비젼

Circuit

division

주요 연구

Design Technology for VLSI and PIM, Computational Lithography

소속연구실

반도체 설계 기술 연구실

위치

전기및전자공학부동 (E3-2)

6206

연락처

3479

이메일

youngsoo-p@kaist.ac.kr

웹사이트

http://dtlab.kaist.ac.kr/

학위

Ph.D. (2000) Seoul National Univ.

대표업적

“Pulse width allocation and clock skew scheduling: optimizing sequential circuits based on pulsed latches,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 29, no. 3, pp. 355-366, Mar. 2010.
“Power gating: circuits, design methodologies, and best practice for standard-cell VLSI designs,” ACM Transactions on Design Automation of Electronic Systems, vol. 15, no. 4, article 28, pp. 28:1-28:37, Sep. 2010.
“Retiming pulsed-latch circuits with regulating pulse width,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 30, no. 8, pp. 1114-1127, Aug. 2011.
“Synthesis of active-mode power-gating circuits,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 31, no. 3, pp. 391-403, Mar. 2012.
“Clock gating synthesis of pulsed-latch circuits,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 31, no. 7, pp. 1019-1030, July 2012.