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It is a fait accompli that the end of shrinking era for VLSI chips that was fueled by Moore’s Law is looming over the horizon as CMOS technology is approaching its limits with respect to chip integration density, speed, and power consumption. Over the past twenty years, my research group has developed innovative circuits and CAD tools for the Beyond Moore’s Law technologies that rely on (i) quantum tunneling in transistors, nanowires, and quantum boxes; ionic transport through complex metal oxide films; (iii) strain-assisted spin-polarized electron tunneling through paramagnetic material, and (iv) spoof surface plasmon polariton (SSPP) mode slow electromagnetic wave propagation through specially-engineered structures. These emerging technologies augur a revolutionary shift of design paradigms for integrated circuits and CAD tools that must account for quantum effects in nanoscale devices as well as local interactions between circuit elements in unconventional architectures. To illustrate the advantages of emerging nanoelectronics, I shall discuss two specific examples of non-Boolean architectures: visual computing by cellular ensemble arrays comprising spatially-distributed quantum boxes, and neuromorphic computing by spike timing-dependent plasticity (STDP) learning networks comprising oxide-based analog synaptic devices. I shall also briefly discuss a promising terahertz technology that utilizes slowed-down electromagnetic waves over metamaterial structures to perform Boolean functions at THz as well as 50 GHz analog-to-digital conversion.
Professor Pinaki Mazumder received his PhD in Electrical and Computer Engineering from the University of Illinois at Urbana-Champaign in 1988 after he receved his MS degree in Computer Science from University of Alberta in Canada, BS degree in Electrical Engineering from Indian Institute of Science at Bangalore, and BSc Physics Honors degree from Guwahati University in India. He is a professor of electrical engineering and computer science at the University of Michigan where he has been teaching for the past 26 years. He spent 3 years at National Science Foundation serving as the lead program manager of Emerging Models and Technologies (MET) program in the CISE Directorate as well as leading the quatum, molecular and high-performance simulation (QMHPS) program in the Engineering Directorate. He worked for 6 years at AT&T Bell Laboratories in USA and BEL in India, and spent his sabbatical year at Stanford University, University of California at BBerkeley and NTT Center Research Laboratory in Japan. He has published over 250 technical papers and 4 books on various aspects of VLSI systems. In evolutionary CMOS research, Prof. Mazumder solved numerous use-inspired research problems that were at least ten years ahead of their time and eventually Moore’s Law as vindicated the practical merits of his research in CMOS technology. To wit: his research in testable DRAM circuits, in-line accelerated testing procedures for high-density RAM chips, and testing of embedded ROM and SRAM through JEDEC boundary scan prots are widely used in commercial chips by semiconductor random-access memory and FPGA manufacturers. In revolutionary emerging technologies, Professor Mazumder has made sustained impact for the past 20 years in CAD tools and circuit designs for emerging technologies including quantum MOS, spintronics, spoof plasmonics, and resonant tunneling devices. Prof. Mazumder is a AAAS Fellow (2007) and an IEEE Fellow (1999) for his distinguished contributions to the field of VLSI.
Copyright ⓒ 2015 KAIST Electrical Engineering. All rights reserved. Made by PRESSCAT
Copyright ⓒ 2015 KAIST Electrical Engineering. All rights reserved. Made by PRESSCAT
Copyright ⓒ 2015 KAIST Electrical
Engineering. All rights reserved.
Made by PRESSCAT
