Machine intelligence has been improving significantly with explosive interest in deep learning. Machines are now a match for humans at the functionality in some specific applications, but the energy-efficiency of today’s computing platforms running deep learning models is not comparable to that of the human brain. Neuromorphic hardware has drawn attention as an approach to deal with the issues of today’s computing platforms based on Von Neumann architecture when running deep learning models, but large-scale deep neural networks such as AlexNet have not been demonstrated yet in any neuromorphic systems. Since 2014, we have been developing a non-Von Neumann computing system called INSight based on data flow architecture that aims at running large-scale deep neural networks in the neuromorphic fashion. We have now reached a major milestone and will demonstrate INSight running the convolutional layers of AlexNet. The proposed system is implemented with Xilinx Virtex 7 FPGA and performs the processing using 100K synapses mapped on LUTs without any array-type memories. It processes 1552 images per second and consumes 7.2W, resulting in the state-of-the-art energy efficiency on FPGA.
Jaeyong Chung is an Assistant Professor in the Department of Electronic Engineering at Incheon National University, Incheon, Korea. He received the B.S. degree in electrical engineering from Yonsei University, Seoul, Korea, in 2006, and the M.S. and Ph.D. degrees in electrical and computer engineering from the Department of Electrical and Computer Engineering, University of Texas, Austin, in 2008 and 2011, respectively. He worked at Strategic CAD Lab (SCL), Intel and IBM T.J. Watson Research Center during the summers of 2008 and 2010, respectively. From 2011 to 2013, he was with the Design Compiler Team at Synopsys, Inc., Mountain View, CA. His current research interests include neuromorphic systems and deep learning.
Prof. Chung was the recipient of best paper award nominations at the International Conference on Computer-Aided Design (ICCAD) in 2009 and the Asia and South Pacific Design Automation Conference (ASPDAC) in 2011. One of his co-authored papers is selected in the Asian Test Symposium (ATS) 20th Anniversary Compendium.