There is a set of supply voltage (Vdd) and threshold voltages (Vthn and Vthp), which is called “Minimum Energy Point (MEP),” that leads to the minimum energy consumption per operation under a specified timing constraint. First, simulated MEP loci in a Vdd-Vth space will be shown for a model circuit and a processor. The shape of the locus suggest us an effective strategy for DVFS and ABB. Then a measured MEP locus of an on-chip memory will be explained together with the standard-cell based structure of the memory for stable operation under a lower supply voltage for reducing energy consumption.
Next, an algorithm for MEP tracking will be introduced. MEP operation requires information on operating conditions such as Vth and temperature together with threshold-voltage control capability. Ring-oscillator-based on-chip monitors and a body-bias-generator compatible with cell-based design will be discussed.
Hidetoshi Onodera received the B.E., and M.E., and Dr. Eng. degrees in Electronic Engineering, all from Kyoto University, Kyoto, Japan.
He joined the Department of Electronics, Kyoto University, in 1983, and currently a Professor in the Department of Communications andComputer Engineering, Graduate School of Informatics, Kyoto University.
His research interests include design technologies for Digital, Analog, and RF LSIs, with particular emphasis on low-power design, design formanufacturability, and design for dependability.
Dr. Onodera served as the Program Chair and General Chair of ICCAD in 2003 and 2004, respectively, and those of ASP-DAC in 2006 and 2007.
He served as an Editor-in-Chief of IEICE Transactions on Electronics and that of IPSJ Transactions on System LSI Design methodology.
He was Chairs of IEEE SSCS Kansai Chapter, IEEE CAS Kansai Chapter, and IEEE Kansai Section.
Currently he is serving as the VP of Awards in CEDA executive committee.