Bayesian Optimization of MOSFET Devices Using Effective Stopping Condition

제목: Bayesian Optimization of MOSFET Devices Using Effective Stopping Condition

논문지, 연도: IEEE Access, 2021

저자: Bokyeom Kim and Mincheol Shin

초록: Current nanometer-scale metal-oxide-semiconductor field-effect transistor (MOSFET) devices exhibit short-channel, quantum, and self-heating effects, making modeling and analysis very complex. A few recent works have employed machine-learning (ML) techniques and neural networks (NN) to model the complex relationships and optimize devices, but a problem with the NN-based device optimization is that it is data-intensive. Bayesian optimization (BO) can realize ML-based data-efficient optimization of the MOSFET device, as it finds the global optimum while requiring few training data. BO stops theoretically when every candidate is explored, so previous works used a fixed number of iterations for the stopping condition. Such an empirical stopping condition is detrimental to the efficiency and reliability of BO, because the global optimum can be found at an earlier stage or even after stopping. Recently, maximum expected improvement (EI max ) with a tiny constant has been proposed as a stopping condition for BO. However, there have not been sufficient works for improving efficiency of BO. By advancing the EI max scheme, we have systemically investigated the effective stopping condition (ESC) for BO of MOSFET devices to boost the efficiency and reliability of optimization. We found that EI max less than a 1% of unit value was an efficient and reliable ESC for optimization, which resulted in up-to-87.6% and up-to-47% reductions of required training data compared with the fixed iteration method and the tiny constant method, respectively. Our study provides a novel method to boost efficiency and reliability of BOs for the optimization of MOSFET design in the semiconductor industry.



Reliable multilevel memristive neuromorphic devices based on amorphous matrix via quasi-1D filament confinement and buffer layer

Title: Reliable multilevel memristive neuromorphic devices based on amorphous matrix via quasi-1D filament confinement and buffer layer      

Conference/Journal, Year: Science Advances, 2022

Author: Sang Hyun Choi, See-On Park, Seokho Seo, and Shinhyun Choi

Abstract: Conductive-bridging random access memory (CBRAM) has garnered attention as a building block of non–von Neumann architectures because of scalability and parallel processing on the crossbar array. To integrate CBRAM into the back-end-of-line (BEOL) process, amorphous switching materials have been investigated for practical usage. However, both the inherent randomness of filaments and disorders of amorphous material lead to poor reliability. In this study, a highly reliable nanoporous–defective bottom layer (NP–DBL) structure based on amorphous TiO2 is demonstrated (Ag/a-TiO2/a-TiOx/p-Si). The stoichiometries of DBL and the pore size can be manipulated to achieve the analog conductance updates and multilevel conductance by 300 states with 1.3% variation, and 10 levels, respectively. Compared with nonporous TiO2 CBRAM, endurance, retention, and uniformity can be im-proved by 106 pulses, 28 days at 85°C, and 6.7 times, respectively. These results suggest even amorphous-based systems, elaborately tuned structural variables, can help design more reliable CBRAMs.


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Neural Network Physically Unclonable Function: A Trainable Physically Unclonable Function System with Unassailability against Deep Learning Attacks Using Memristor Array

Title: Neural Network Physically Unclonable Function: A Trainable Physically Unclonable Function System with Unassailability against Deep Learning Attacks Using Memristor Array

Conference/Journal, Year: Advanced Intelligent Systems, 2021

Author: Junkyu Park, Yoonji Lee, Hakcheon Jeong, and Shinhyun Choi


The dissemination of edge devices drives new requirements for security primitives for privacy protection and chip authentication. Memristors are promising entropy sources for realizing hardware-based security primitives due to their intrinsic randomness and stochastic properties. With the adoption of memristors among several technologies that meet essential requirements, the neural network physically unclonable function (NNPUF) is proposed, a novel PUF design that takes advantage of deep learning algorithms. The proposed design integrated with the memristor array can be constructed easily because the system does not depend on write operation accuracy. To contemplate a nondifferentiable module during training, an original concept of loss called PUF loss is devised. Iterations of weight update with the loss function bring about optimal NNPUF performance. It is shown that the design achieves a near-ideal 50% average value for security metrics, including uniformity, diffuseness, and uniqueness. This means that the NNPUF satisfies practical quality standards for security primitives by training with PUF loss. It is also demonstrated that the NNPUF response has an unassailable resistance against deep learning-based modeling attacks, which is verified by the near-50% prediction model accuracy.


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우리 학부 박성욱 교수 연구팀, 인공신경망을 이용한 드론의 이륙각도 감지 기술 개발

우리 학부 박성욱 교수와 박사과정 강현성 학생이 CNN(Convolutional neural network, 인공신경망의 한 종류)으로 MDS (micro-Doppler signature, 드론을 레이더로 감지하기 위한 신호 중 하나)를 분류하여 실제 드론의 이륙 각도를 감지하는 기술을 개발하였습니다.


드론에 대한 기술이 빠르게 발전함에 따라, 농업, 화물 운송, 영상 수집 등 그에 따른 많은 장점도 있으나 불법적으로 드론을 악용하는 사례나 드론으로 인한 사고로 인한 문제점이 늘어가고 있습니다. 이로 인한 문제점을 지속적으로 관리하고 방지하기 위해, 공중에 떠 있는 드론을 정확하게 인식하고 그 위치를 파악하는 연구가 활발하게 진행되고 있습니다. 하지만 현재의 기술은 대부분 수 킬로미터 한정의 레이더 감지가 가능하며, 공간적인 한계를 극복하기 위해 넓게 분포된 저렴한 레이더 네트워크 방식이 쓰였으나 이로 인해 하나의 레이더가 감지해야 할 이륙 각도의 범위가 넓어지게 되었습니다. 하지만 대부분의 레이더는 팬 빔 (fan beam)을 회전시키면서 스캔하므로 정확한 이륙 각도의 감지가 어렵습니다.


본 연구팀은 이러한 레이더의 한계를 극복하면서도 값싼 레이더 네트워크 방식을 유지하기 위해, 드론에서부터 얻을 수 있는 MDS 라는 신호와 CNN (합성곱신경망)을 이용해 드론의 이륙 각도를 비교적 정확하게 분류하는 방식을 개발하였습니다. 또한, 이러한 인공 신경망의 분류 효율을 높이기 위해 다양한 극성 (polarization) 변수도 이용하였습니다. 결과적으로, 극성 변수의 종류를 늘려감에 따라 84.75%의 효율에서 97.9%의 효율까지 정확해진 결과를 발표하였습니다.


본 성과는 “IEEE Geoscience and remote sensing letters” 에 2020년 11월 2일자에 온라인 출판되었습니다. 자세한 내용은 아래 링크에서 확인하실 수 있습니다.





그림: 레이더 네트워크를 이용한 드론 이륙각도 인식에 대한 개요


Conductive-bridging random-access memories for emerging neuromorphic computing

A research article authored by Jun-Hwe Cha (KAIST EE), Sang Yoon Yang (KAIST EE), Jungyeop Oh (KAIST EE), Shinhyun Choi (KAIST EE), Sangsu Park (SK Hynix), Byung Chul Jang (Samsung Electronics), Wonbae Ahn (KAIST EE) and Sung-Yool Choi (KAIST EE; Corresponding author) was published in Nanoscale (2020.07)

Article title: Conductive-bridging random-access memories for emerging neuromorphic computing

With the increasing utilisation of artificial intelligence, there is a renewed demand for the development of novel neuromorphic computing owing to the drawbacks of the existing computing paradigm based on the von Neumann architecture. Extensive studies have been performed on memristors as their electrical nature is similar to those of biological synapses and neurons. However, most hardware-based artificial neural networks (ANNs) have been developed with oxide-based memristors owing to their high compatibility with mature complementary metal–oxide–semiconductor (CMOS) processes. Considering the advantages of conductive-bridging random-access memories (CBRAMs), such as their high scalability, high on–off current with a wide dynamic range, and low off-current, over oxide-based memristors, extensive studies on CBRAMs are required. In this review, the basics of operation of CBRAMs are examined in detail, from the formation of metal nanoclusters to filament bridging. Additionally, state-of-the-art experimental demonstrations of CBRAM-based artificial synapses and neurons are presented. Finally, CBRAM-based ANNs are discussed, including deep neural networks and spiking neural networks, along with other emerging computing applications. This review is expected to pave the way toward further development of large-scale CBRAM array systems.


교수 Nanoscale 0

Shinhyun Choi's Research Laboratory [Memristor for AI]


Memristor for AI

Memristor, also called RRAMs, have attracted tremendous attention as a candidate for machine learning, neuromorphic computing and artificial intelligence. Memristor has two terminals structure, which allows the device to be fabricated into large crossbar array. Moreover, a single memristor has an analog switching behavior unlike conventional devices such as CMOS based processor. Due to these characteristics, effective matrix operation is possible through memristor array, which makes the memristor adequate as a device for deep learning process and artificial intelligence. The inherent memory effect of memristor removes bottlenecks between memory and processor unit, existing on conventional AI processor. Other properties such as high scalability, low power consumption and fast switching speed are the remarkable strength of memristor for AI and deep learning applications.


Research area of Emerging Nano Technology and Integrated Systems Lab (ENTIS)

Our lab focuses are 1) to overcome the limitations of conventional memristor and 2) to develop memristor-based platform for various deep neural network(DNN), spiking neural network(SNN) and other applications.

1. Memristor Devices Development

Conventional memristors suffer from unavoidable spatial-temporal variation due to uncontrollable, stochastic filament formation. Our Lab is now developing a new strategy to achieve uniform switching through CMOS compatible materials/fabrication steps as well as linearity, retention and endurance.


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2. Artificial Neural Network Simulation using memristor

To optimize Memristor devices for Artificial Neural Network (ANN) algorithm such as Deep Neural Network (DNN) and Spiking Neural Network (SNN), our Lab is simulating memristor devices arrays using software reflecting hardware conditions.


3. Artificial Neural Network System Design and Integration

Our lab designs artificial neural network system on customized PCB board and integrated chip based on memristor device utilized as an AI hardware. The goal is developing large-scale neural network array for AI hardware processing big data. Another aim is integration of the system, broadening the application of memristor-based ANN system.


Monolithic integration of GaAs//InGaAs photodetectors for multicolor detection

Prof. Sanghyeon Kim’s paper on the multi-color photodetector, which can be used as a compact photonic sensor for AI chip was presented in VLSI symposia 2019*.

*VLSI symposia is the one of flagship conference in VLSI society.

Title: Monolithic integration of GaAs//InGaAs photodetectors for multicolor detection

Multicolor photodetectors (PDs) by using bulk p-i-n based visible GaAs and near-infrared (IR) InGaAs PD was successfully fabricated via monolithic integration by wafer bonding and epitaxial lift-off. It showed high-performance individual operation comparable to that of bulk PDs with tight vertical alignment on a single substrate for future high-resolution multicolor PDs. At the same time, it covered a broad wavelength range from visible to IR.




Figure 1. Multi-Color Photodetector

Large-Scale, Low-Power Nonvolatile Memory Based on Few-Layer MoS2 and Ultrathin Polymer Dielectrics

A research article authored by Sang Cheol Yang (KAIST EE), Junhwan Choi (KAIST CBE), Byung Chul Jang (KAIST EE), Woonggi Hong (KAIST EE), Gi Woong Shim (KAIST EE), Sang Yoon Yang (KAIST EE), Sung Gap Im (KAIST CBE), and Sung‐Yool Choi (KAIST EE; Corresponding author) was published in Advanced Electronic Materials (2019.05)

Article title: Large-Scale, Low-Power Nonvolatile Memory Based on Few-Layer MoS2 and Ultrathin Polymer Dielectrics

With the advent of artificial intelligence and the Internet of Things, demand has grown for flexible, low-power, high-density nonvolatile memory capable of handling vast amounts of information. Ultrathin-layered 2D semiconductor materials such as molybdenum disulfide (MoS2) have considerable potential for flexible electronic device applications because of their unique physical properties. However, development of flexible MoS2-based flash memory is challenging, as there is a lack of flexible dielectric materials with sufficient insulating properties for use in flash memory devices with dielectric bilayers. Here, large-scale, low-power nonvolatile memory is realized based on a chemical vapor deposition (CVD)-grown millimeter-scale few-layer MoS2 semiconductor channel and polymer dielectrics prepared via an initiated CVD (iCVD) process. Using the outstanding insulating properties and solvent-free nature of iCVD, fabricated memory devices with a tunable memory window, a high on/off ratio (≈106), low operating voltages (≈13 V), stable retention times exceeding 105 s with a possible extrapolated duration of years, and cycling endurance exceeding 1500 cycles are demonstrated. Owing to these characteristics, these devices distinctly outperform previously reported MoS2-based memory devices. Leveraging the inherent mechanical flexibility of both ultrathin polymer dielectrics and MoS2, this work is a step toward realization of large-scale, low-power, flexible MoS2-based flash memory.


Figure 1. A Schematic illustration of fabricated MoS2-based memory device composed of pV3D3 tunneling dielectric, Au nanoparticle (NP) FG, and pC1D1 blocking dielectric layer. B Cross-sectional HRTEM image of memory device. C Optical microscopy image of fabricated 5 × 6 memory device array. D Transfer curves as functions of pulse width during erasing operation.

A Recoverable Synapse Device Using a Three-Dimensional Silicon Transistor

A research article authored by Jae Hur (KAIST EE), Byung Chul Jang (KAIST EE), Jihun Park (KAIST EE), Dong-Il Moon (KAIST EE), Hagyoul Bae (KAIST EE), Jun-Young Park (KAIST EE), Gun-Hee Kim (KAIST EE), Seung-Bae Jeon (KAIST EE), Myungsoo Seo (KAIST EE), Sungho Kim (KAIST EE), Sung-Yool Choi (KAIST EE; Corresponding author), and Yang-Kyu Choi (KAIST EE; Corresponding author) was published at Advanced Functional Materials (2018.11)

Article title: A Recoverable Synapse Device Using a Three-Dimensional Silicon Transistor

To prepare for the upcoming big-data era, numerous attempts are underway to develop a neuromorphic system which is capable of imitating a biologic neural network. Despite the significant improvements to software-based artificial neural networks (ANNs) recently, they remain inefficient in terms of energy use. Alternatively, many researchers have been attracted to hardware-based ANNs by fundamentally mimicking neural circuits and synapses. In this study, a two-terminal silicon-channel synapse (SINAPSE) with a poly-Si/SiO2/Si3N4 gate stack over a silicon channel is introduced, and demonstrated the smallest size of a synapse device reported thus far, along with reliable, low-power performance. A distinctive feature of SINAPSE is that it emulates synaptic recovery, a retrieval process for neurotransmitters which would be otherwise depleted. By applying an electrical recovery pulse to SINAPSE, synaptic recovery was for the first time successfully imitated. Experimental results demonstrate the potential of the curable SINAPSE as a fundamental unit in neuromorphic circuitry.


Figure 1. A A schematic illustration of a synapse between a presynaptic and postsynaptic neuron in a biological system. B A schematic of the SINAPSE structure and the electron trajectories during the potentiation and depression processes of the charge-trap nitride of SINAPSE. C Cross-sectional TEM images of SINAPSE along the silicon nanowire direction (left-side panel) and along the gate direction (right-side panel). D Analog conductance modulation behavior of SINAPSE as a function of the number of applied pulse cycles. (Inset) Applied presynaptic voltage schemes for potentiation and depression. E Learned weights map with the ANN, which is based on a SINAPSE device with 100 output neurons. F Recognition rate as a function of the number of the number of training instances. G Recovery (Vpulse = 6 V and tpulse = 1 ms) results for SINAPSE after fatigue.

Zero-static-power nonvolatile logic-in-memory circuits for flexible electronics

A research article authored by Byung Chul Jang (KAIST EE), Sang Yoon Yang (KAIST EE), Hyejeong Seong (KAIST CBE), Sung Kyu Kim (KAIST MSE), Junhwan Choi (KAIST CBE), Sung Gap Im (KAIST CBE), and Sung-Yool Choi (KAIST EE; Corresponding author) was published at Nano Research (2017.07)

Article title: Zero-static-power nonvolatile logic-in-memory circuits for flexible electronics

Flexible logic circuits and memory with ultra-low static power consumption are in great demand for battery-powered flexible electronic systems. Here, we show that a flexible nonvolatile logic-in-memory circuit enabling normally-off computing can be implemented using a poly(1,3,5-trivinyl-1,3,5-trimethyl cyclotrisiloxane) (pV3D3)-based memristor array. Although memristive logic-in-memory circuits have been previously reported, the requirements of additional components and the large variation of memristors have limited demonstrations to simple gates within a few operation cycles on rigid substrates only. Using memristor-aided logic (MAGIC) architecture requiring only memristors and pV3D3-memristor with good uniformity on a flexible substrate, for the first time, we experimentally demonstrated our implementation of MAGIC-NOT and -NOR gates during multiple cycles and even under bent conditions. Other functions, such as OR, AND, NAND, and a half adder, are also realized by combinations of NOT and NOR gates within a crossbar array. This research advances the development of novel computing architecture with zero static power consumption for battery-powered flexible electronic systems.


Figure 1. A Schematic illustration of a pV3D3-memristor with an 8 × 8 crossbar array on a plastic substrate. The inset with the orange dotted line shows the logical states of the pV3D3-memristor, the inset with the green dotted line shows the molecular structure of pV3D3, and the inset with the black dotted line depicts the feasible logic gates using the pV3D3-memristor. B Photograph of a flexible pV3D3-memristor on a PES substrate. The inset shows a magnified optical image of the flexible pV3D3-memristor array (scale bar: 20 μm). C MAGIC-NOR gate within the crossbar array and its equivalent circuit. D Experimental results of the MAGIC-NOR gate for all input memristor combinations during 50 cycles.