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Prof. Sung-Ju Lee and Prof. Jinwoo Shin developed an new AI technology and present upcoming NeurIPS 2022
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KAIST PhD candidate Yuji Roh from the School of Electrical Engineering (advisor: Prof. Steven Euijong Whang) was selected as a recipient of the 2022 Microsoft Research PhD Fellowship.
[Yuji Roh]
The list of recipients: https://www.microsoft.com/en-us/research/academic-program/phd-fellowship/2022-recipients/
Interview (Asia): https://www.youtube.com/watch?v=qwq3R1XU8UE
[Prof. Joungho Kim, Hyunwook Park, from left]
-Award Name: Best Poster Award
-Paper Title: Scalable Transformer Network-based Reinforcement Learning Method for PSIJ Optimization in HBM
-Authors: Hyunwook Park, Taein Shin, Seongguk Kim, Daehwan Lho, Boogyo Sim, Jinouk Song, Kyu-Bong, and Joungho Kim (Corresponding author)
-Conference Name: 2022 IEEE 31th Conference on Electrical Performance of Electronic Packaging and Systems
-Time of the event: 9 to 12th October, 2022 at San Jose, CA, USA
KAIST EE Postdoc researcher Hyunwook Park (under the supervision of Professor Joungho Kim) won the Best Poster Award at 2022 IEEE 31th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS Conference), which was held at San Jose, California, from 9 to 12th October.
EPEPS Conference is an annual academic conference in which many prestigious universities and companies share their research works in the field of signal and power integrity-based semiconductor.
Postdoc researcher Researcher Hyunwook Park presented the paper “Scalable Transformer Network-based Reinforcement Learning Method for PSIJ Optimization in HBM”, which was nominated for the Best Poster Award thanks to its excellence.
[Prof. Junil Choi]
EE Professor Junil Choi was awarded the Early Achievement Award by the IEEE Communications Society Communication Theory Technical Committee (CTTC), becoming the first Korean member to receive the honor.
Although professor Choi was chosen as the recipient for the 2021 award, the award ceremony was held at the belated Communication Theory Workshop (CTW) last week, due to the COVID-19 pandemic.
The IEEE CTTC was established in 1964 as one of the first technical committees within the IEEE Communications Society (ComSoc).
Since 2016, the CTTC Early Achievement Award has celebrated the achievements of members with early career visibility within 10 years of their Ph.D., with a history of recipients from prestigious institutions such as Stanford University, Imperial College London, Virginia Tech and KTH.
[Prof. Minsoo Rhu]
[Award picture of MICRO Hall of Fame]
Related links:
MICRO: https://www.microarch.org/micro55
MICRO Hall of Fame: https://www.sigmicro.org/awards/microhof.php
[Prof. Hyun-Sik Kim, PhD candidate Gyuwan Lim, PhD candidate Gyeong-Gu Kang, from left]
EE professor Hyun-Sik Kim’s team of Ph.D. students received the Prime Minister’s Award at the 23rd Korea Semiconductor Design Challenge.
The 23rd Korea Semiconductor Design Challenge is held to cultivate design skills and discover creative ideas of students within the field of semiconductor design, jointly organized by the Korean Ministry of Trade, Industry and Energy, and the Korea Semiconductor Industry Association (KSIA).
The winners, Gyuwan Lim and Gyeong-Gu Kang, have been selected for the achievement of high resolution and high uniformity with their mobile device Display Driver IC (DDI) design while maintaining an ultra-small chip area.
The DDI chip is a key component of a display system, that converts digital display data into analog signals (digital-to-analog conversion, DAC) and writes them to the display panel. The KAIST team solved the problem of uniformity and increasing chip surface that comes with higher resolution DDI chips.
The award-winning DDI chip design consists of a low-voltage MOSFET with a voltage amplifier instead of the conventional high-voltage MOSFET. This technology dramatically reduces the channel area, further reduced through a novel LSU technology that generates a 10-bit output voltage from an 8-bit input voltage.
The team was able to achieve high uniformity through designing a robust amplifier and chip operation against variations of the CMOS fabrication process. The novel DDI chip design is expected to significantly reduce cost while increasing the quality of mobile device displays through the reduced chip area, while achieving high resolution and high uniformity at the same time.
The results of this study were also presented at ISSCC 2022, a highly reputable international conference in the field of integrated circuits.
[Prof. Myoungsoo Jung, Miryeong Kwon, Seungjun Lee, and Hyunkyu Cho from left]
Our department’s Professor Myoungsoo Jung’s research team has developed the world’s first Predictable Latency Mode (PLM) SSD based hardware and software co-designed framework for Log-Structured Merge Key-Value Stores (LSM KV store).
The research team has developed the ‘hardware and software co-designed framework for LSM KV store, Vigil-KV’ that eliminates long-tail latency by utilizing the Predictable Latency Mode (PLM) interface, which provides constant read latency, to the actual datacenter-scale SSD. Vigil-KV outpoerforms 3.19x faster tail latency and 34% faster average latency compared to the existing LSM KV store.
LSM KV store, a kind of database, is used to manage various application data, and it must process the user requests within the requirement time in order not to degrade the user experience. To this end, Vigil-KV enables a predictable latency mode (PLM) interface on an actual datacenter-scale NVMe SSD (PLM SSD), which guarantees constant read latency in deterministic mode related to read service without performing SSD’s internal tasks.
Specifically, Vigil-KV hardware makes the deterministic mode SSDs exist in the system to remove SSD’s internal tasks by configuring PLM SSD RAID. In addition, Vigil-KV software prevents the deterministic mode from being released by LSM KV store’s internal tasks, scheduling LSM KV store operations (e.x., compaction/flush operations) and client requests.
Among the proposed research results, especially noteworthy is that Vigil-KV is the first work that implements the PLM interface in a real SSD and makes the read latency of LSM KV store deterministic in a hardware-software co-design manner. They prototype Vigil-KV hardware on a 1.92TB datacenter-scale NVMe SSD while implementing Vigil-KV software using Linux 4.19.91 and RocksDB 6.23.0.
The KAIST Ph.D. Candidates (Miryeong Kwon, Seungjun Lee, and Hyunkyu Choi) participate in this research, and the paper (Vigil-KV: Hardware-Software Co-Design to Integrate Strong Latency Determinism into Log-Structured Merge Key-Value Stores) was reported in July, 11th at ‘USENIX Annual Technical Conference, ATC, 2022’. In addition, they has won the Best Paper Award from Samsung for this paper (Vigil-KV) with Professor Jae-Hyeok Choi’s research team.
The Best Paper Award from Samsung recognizes master’s and doctorate students that participated in research grant projects and published papers related to the project among papers adopted by foreign journals/conferences since September 21st. This year’s awards consisted of grand award (2 people), excellence award (1 person), and encouragement award (2 people).
The research was supported by Samsung. More information on this paper can be found at http://camelab.org.
[Prof. Kayoung Lee]
KAIST EE Professor Kayoung Lee is selected for the Young Scholar Award at the 9th Korean Symposium on Graphene and 2D Materials, hold by the Korean Graphene Society.
The Young Scholar Award is awarded to those who have made a great contribution to the Korean graphene and 2D materials field, among academics under the age of 40.
Professor Kayoung Lee, as this year’s awardee, received the award with a prize of 1 million wons.
[Award ceremony picture, Society Chair, Prof. Jong-Hyun Anh, Prof. Kayoung Lee, from left ]