Prof. John Kim has been elevated to IEEE Fellow, class of 2025, “for contributions to the design and analysis of high-performance interconnection network architectures.” Prof. Kim’s research area is in computer architecture and interconnection networks. As systems scale-up and scale-out with more components, data movement is becoming a bigger bottleneck in modern digital systems. Prof. Kim’s research addresses the communication bottleneck in multi-core and large-scale systems and his research lab is also currently exploring communication bottlenecks in deep-learning systems.
Prof. Kim’s research has led him to become the first researcher from Asia to be inducted into the hall-of-fame for all three main computer architecture conferences — ISCA, MICRO, and HPCA. He was also the first researcher from an Asia institution to serve as the program chair for a top-tier computer architecture conference (HPCA’24). Prof. Kim plans on pursuing research on efficient data movement across memory-centric architectures and exploiting domain-specific networks.
< Photo. The research team of the School of Electrical Engineering posed by the newly deveoped processor. (From center to the right) Professor Young-Gyu Yoon, Integrated Master’s and Doctoral Program Students Seungjae Han and Hakcheon Jeong and Professor Shinhyun Choi >
Existing computer systems have separate data processing and storage devices, making them inefficient for processing complex data like AI. EE research team has developed a memristor-based integrated system similar to the way our brain processes information. It is now ready for application in various devices including smart security cameras, allowing them to recognize suspicious activity immediately without having to rely on remote cloud servers, and medical devices with which it can help analyze health data in real time.
The joint research team of Professor Shinhyun Choi and Professor Young-Gyu Yoon of the School of Electrical Engineering has developed a next-generation neuromorphic semiconductor-based ultra-small computing chip that can learn and correct errors on its own.
< Figure 1. Scanning electron microscope (SEM) image of a computing chip equipped with a highly reliable selector-less 32×32 memristor crossbar array (left). Hardware system developed for real-time artificial intelligence implementation (right). >
What is special about this computing chip is that it can learn and correct errors that occur due to non-ideal characteristics that were difficult to solve in existing neuromorphic devices. For example, when processing a video stream, the chip learns to automatically separate a moving object from the background, and it becomes better at this task over time.
This self-learning ability has been proven by achieving accuracy comparable to ideal computer simulations in real-time image processing. The research team’s main achievement is that it has completed a system that is both reliable and practical, beyond the development of brain-like components.
The research team has developed the world’s first memristor-based integrated system that can adapt to immediate environmental changes, and has presented an innovative solution that overcomes the limitations of existing technology.
< Figure 2. Background and foreground separation results of an image containing non-ideal characteristics of memristor devices (left). Real-time image separation results through on-device learning using the memristor computing chip developed by our research team (right). >
At the heart of this innovation is a next-generation semiconductor device called a memristor*. The variable resistance characteristics of this device can replace the role of synapses in neural networks, and by utilizing it, data storage and computation can be performed simultaneously, just like our brain cells.*Memristor: A compound word of memory and resistor, next-generation electrical device whose resistance value is determined by the amount and direction of charge that has flowed between the two terminals in the past.
The research team designed a highly reliable memristor that can precisely control resistance changes and developed an efficient system that excludes complex compensation processes through self-learning. This study is significant in that it experimentally verified the commercialization possibility of a next-generation neuromorphic semiconductor-based integrated system that supports real-time learning and inference.
This technology will revolutionize the way artificial intelligence is used in everyday devices, allowing AI tasks to be processed locally without relying on remote cloud servers, making them faster, more privacy-protected, and more energy-efficient.
“This system is like a smart workspace where everything is within arm’s reach instead of having to go back and forth between desks and file cabinets,” explained KAIST researchers Hakcheon Jeong and Seungjae Han, who led the development of this technology. “This is similar to the way our brain processes information, where everything is processed efficiently at once at one spot.”
The research was conducted with Hakcheon Jeong and Seungjae Han, the students of Integrated Master’s and Doctoral Program at KAIST School of Electrical Engineering being the co-first authors, the results of which was published online in the international academic journal, Nature Electronics, on January 8, 2025. *Paper title: Self-supervised video processing with self-calibration on an analogue computing platform based on a selector-less memristor array ( https://doi.org/10.1038/s41928-024-01318-6 )
This research was supported by the Next-Generation Intelligent Semiconductor Technology Development Project, Excellent New Researcher Project and PIM AI Semiconductor Core Technology Development Project of the National Research Foundation of Korea, and the Electronics and Telecommunications Research Institute Research and Development Support Project of the Institute of Information & communications Technology Planning & Evaluation.
< Photo 1. (From top left) Professor Hyunjoo J. Lee, Dr. Mi-Young Son, Dr. Mi-Ok Lee (In the front row from left) Doctoral student Kiup Kim, Doctoral student Youngsun Lee >
The EE research team led by Professor Hyunjoo J. Lee in collaboration with Dr. Mi-Young Son and Dr. Mi-Ok Lee at Korea Research Institute of and Biotechnology (KRIBB has developed a highly stretchable protruding microelectrode array platform for non-invasive electrophysiological signal measurement of organoids.
Organoids* are highly promising models for human biology and are expected to replace many animal experiments. Their potential applications include disease modeling, drug screening, and personalized medicine as they closely mimic the structure and function of humans. *Organoids: three-dimensional in vitro tissue models derived from human stem cells
Despite these advantages, existing organoid research has primarily focused on genetic analysis, with limited studies on organoid functionality. For effective drug evaluation and precise biological research, technology that preserves the three-dimensional structure of organoids while enabling real-time monitoring of their functions is needed. However, it’s challenging to provide non-invasive ways to evaluate the functionalities without incurring damage to the tissues. This challenge is particularly significant for electrophysiological signal measurement in cardiac and brain organoids since the sensor needs to be in direct contact with organoids of varying size and irregular shape. Achieving tight contact between electrodes and the external surface of the organoids without damaging the organoids has been a persistent challenge.
< Figure 1. Schematic image of highly stretchable MEA (sMEA) with protruding microelectrodes. >
Prof. Hyunjoo J. Lee’s research team developed a highly stretchable microelectrode array with a unique serpentine structure that contacts the surface of organoids in a highly conformal fashion. They successfully demonstrated real-time measurement and analysis of electrophysiological signals from two types of electrogenic organoids (heart and brain). By employing a micro-electromechanical system (MEMS)-based process, the team fabricated the serpentine-structured microelectrode array and used an electrochemical deposition process to develop PEDOT:PSS-based protruding microelectrodes. These innovations demonstrated exceptional stretchability and close surface adherence to various organoid sizes. The protruding microelectrodes improved contact between organoids and the electrodes, ensuring stable and reliable electrophysiological signal measurements with high signal-to-noise ratios (SNR).
< Figure 2. Conceptual illustration, optical image, and fluorescence images of an organoid captured by the sMEA with protruding microelectrodes.>
Using this technology, the team successfully monitored and analyzed electrophysiological signals from cardiac spheroids of various sizes, revealing three-dimensional signal propagation patterns and identifying changes in signal characteristics according to size. They also measured electrophysiological signals in midbrain organoids, demonstrating the versatility of the technology. Additionally, they monitored signal modulations induced by various drugs, showcasing the potential of this technology for drug screening applications.
Prof. Hyunjoo Jenny Lee stated, “By integrating MEMS technology and electrochemical deposition techniques, we successfully developed a stretchable microelectrode array adaptable to organoids of diverse sizes and shapes. The high practicality is a major advantage of this system since the fabrication is based on semiconductor fabrication with high volume production, reliability, and accuracy. This technology that enables in situ, real-time analysis of states and functionalities of organoids will be a game changer in high-through drug screening.”
This study led by Ph.D. candidate Kiup Kim from KAIST and Ph.D. candidate Youngsun Lee from KRIBB, with significant contributions from Dr. Kwang Bo Jung, was published online on December 15, 2024 in Advanced Materials (IF: 27.4).
< Figure 4. Drug screening using cardiac spheroids and midbrain organoids.>
This research was supported by a grant from 3D-TissueChip Based Drug Discovery Platform Technology Development Program (No. 20009209) funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea), by the Commercialization Promotion Agency for R&D Outcomes (COMPA) funded by the Ministry of Science and ICT (MSIT) (RS-2024-00415902), by the K-Brain Project of the National Research Foundation (NRF) funded by the Korean government (MSIT) (RS-2023-00262568), by BK21 FOUR (Connected AI Education & Research Program for Industry and Society Innovation, KAIST EE, No. 4120200113769), and by Korea Research Institute of Bioscience and Biotechnology (KRIBB) Research Initiative Program (KGM4722432).
Ferroelectric materials are being highlighted as a key material for the development of next-generation semiconductor technologies due to their characteristic of storing charges well, making them comparable to a “material that remembers electricity.” The KAIST research team has succeeded in developing high-performance, high-density next-generation memory devices that overcome the limitations of DRAM and NAND Flash memory, the two pillars of the current memory semiconductor industry.
EE Professor Sanghun Jeon’s research team has developed next-generation memory and storage memory technology using hafnia-based ferroelectric materials*. *Hafnia-Based Ferroelectric Material: A non-volatile insulating material actively researched as a core material for next-generation semiconductors, with excellent physical properties such as compatibility with CMOS processes, high speed, and durability.
DRAM memory is a type of volatile memory used to store data in devices such as smartphones, computers, and USB drives. Because of its volatile nature, stored data is lost when external power is cut off. However, it has been used as the main memory due to its low manufacturing cost and high integration density. Despite these advantages, as DRAM memory technology advances, the size of memory cells becomes smaller, reducing the capacity of the storage capacitors that store information. This eventually makes it difficult to sustain memory operation.
The research team focused on overcoming the limitations of these storage capacitors to achieve higher storage capacity in physically small areas. To this end, they developed a hafnia-based ferroelectric ultrathin high-k material. The results showed the lowest reported equivalent oxide thickness (EOT) of 2.4 Å (approximately one ten-thousandth the thickness of a human hair) for DRAM capacitors to date.
The team also developed ferroelectric memory (FRAM), which is being considered as a potential replacement for DRAM. This technology ensures non-volatile data storage and erasure even at low voltages below 1V, significantly improving energy efficiency and making it essential for next-generation memory.
Following advancements in DRAM technology, the team developed next-generation memory technology to overcome the limitations of NAND Flash memory using hafnia-based ferroelectric materials. NAND Flash memory, a non-volatile memory used in devices like smartphones, computers, and USB drives, has evolved to increase storage capacity by stacking multiple layers. However, physical limitations make it challenging to stack more than 500 or 1,000 layers.
<Figure 1. Representative Diagram of Next-Generation DRAM Memory Development Research Schematic illustration of a DRAM memory device and next-generation ferroelectric material-based FRAM memory aimed at drastically increasing the storage capacity of storage capacitors. Ferroelectric materials require low operating voltage and high polarization switching characteristics. Professor Sanghun Jeon’s research team applied two approaches to achieve these goals. As a result, they were the first in the world to simultaneously achieve an operating voltage below 1 V and polarization switching characteristics exceeding 20 μC/cm². Furthermore, they developed a mathematical modeling framework for optimizing vertically stacked 3D 1T-nC FRAM memory.>
In response, the research team applied ferroelectric materials to NAND Flash memory, adding a thin TiO2 interfacial layer to achieve stable data retention in a 3D vertical structure with over 1,000 layers. Furthermore, the team succeeded in developing a high-performance oxide channel-based NAND Flash device, capable of storing more data and maintaining data stability for over 10 years, overcoming the limitations of traditional oxide channel-based memory devices that struggled with complete data erasure.
Professor Jeon stated, “These research results are expected to provide a breakthrough in memory semiconductor technology, which has been stagnant due to scaling issues, and contribute to the commercialization of various AI computing and edge computing technologies in the future.”
< Figure 2. Representative Diagram of Next-Generation Storage Memory Development Research 3D vertically stacked ferroelectric NAND Flash device arrays and gate stack structure. Ferroelectric NAND Flash devices offer low-voltage, high-density performance but are vulnerable to disturbance issues caused by partial polarization switching behavior of ferroelectric materials. Professor Sanghun Jeon’s research team proposed a NAND Flash device gate stack structure incorporating a TiO₂ layer to maximize domain size by considering the free energy of the ferroelectric material. This approach successfully led to the development of high-performance, disturbance-free ferroelectric NAND Flash devices. >
Dr. Venkateswarlu Gaddam, PhD candidates Ki-Wook Kim, Hong-Rae Cho, Jung-Hyun Hwang, Sang-Ho Lee, master’s students Hyo-Jun Choi and Hyun-Jun Kang participated as co-first authors. These research achievements were internationally recognized, with five papers presented at top-tier semiconductor industry conferences in 2024 (2 at VLSI 2024, 3 at IEDM 2024).
“In-depth analysis of the Hafnia ferroelectrics as a key enabler for low voltage & QLC 3D VNAND beyond 1K layers: Experimental demonstration and modeling,” VLSI 2024. DOI: 10.1109/VLSITechnologyandCir46783.2024
“Low-Damage Processed and High-Pressure Annealed High-k Hafnium Zirconium Oxide Capacitors near Morphotropic Phase Boundary with Record-Low EOT of 2.4 Å & high-k of 70 for DRAM,” VLSI 2024. DOI: 10.1109/VLSITechnologyandCir46783.2024
“Unveiling the Origin of Disturbance in FeFET and the Potential of Multifunctional TiO2 as a Breakthrough for Disturb-free 3D NAND Cell: Experimental and Modeling,” IEDM 2024.
“Oxide Channel Ferroelectric NAND Device with Source-Tied Covering Metal Structure: Wide Memory Window (14.3 V), Reliable Retention (> 10 years) and Disturbance Immunity (△Vth ≤ 0.1 V) for QLC Operation,” IEDM 2024.
“Design Methodology for Low-Voltage Operational (≤1 V) FRAM Cell Capacitors and Approaches for Overcoming Disturb Issues in 1T-nC Arrays: Experimental & Modeling,” IEDM 2024.
IEEE VLSI and IEEE IEDM conferences are considered the “Olympics of semiconductors,” where leading companies like Samsung Electronics, SK Hynix, Micron, and Intel, as well as renowned academics, share the latest technological advancements and discuss future directions.
This research was conducted in collaboration with Samsung Electronics and Hanyang University, supported by the Korea Evaluation Institute of Industrial Technology (KEIT), the Ministry of Science and ICT’s Innovation Research Center (IRC) program, and funding from Samsung Electronics.
<Professor Minkyu Je, Recipient of the Minister of Science and ICT Commendation>
Professor Minkyu Je from our department was recognized for his contributions to the advancement of the AI semiconductor industry through the development of innovative neural network computation circuits and system technologies based on embedded Magnetoresistive Random Access Memory (eMRAM) Process-In-Memory (PIM) technology. He was awarded a commendation from the Ministry of Science and ICT at the Future Technology Conference on AI Semiconductors held on December 20.
Since April 1, 2022, Professor Je’s research team at the Integrated Memory & Processor Architecture for Compact Systems (IMPACT) Lab has been working on the “Development of Core Technologies for High-Efficiency AI Semiconductors Utilizing eMRAM-based PIM Technology” project, supported by the Ministry of Science and ICT and supervised by the Institute for Information & communication Technology Planning & evaluation. Through this project, the team has achieved remarkable results. These include the development of neural network computation circuit technology that consumes low power, allows for adjustable computational precision, and improves memory utilization efficiency by more than twofold compared to existing technologies. They also developed a weight representation method and supporting circuit architecture that reduce computational errors caused by analog variations during in-memory analog computation, while simultaneously reducing power consumption. Furthermore, they introduced an efficient analog neural network accelerator technology capable of processing the entire neural network computation within a PIM-based System-on-Chip (SoC). This technology is robust against computational errors due to analog variations and can be applied to large-scale neural network models without retraining.
Master’s candidate Taesoo Kim from Professor Jeongho Kim’s lab achieved remarkable success by winning the Best Paper Award at the ‘IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) 2024‘, held on December 17-19 at the Taj Yeshwantpur, in Bangalore, India.
The ‘IEEE EDAPS’ is the largest and most influential conference on semiconductor packaging technology in the Asia-Pacific region. Since 2002, it has been annually organized and hosted by the IEEE Electronic Packaging Society.
< Taesoo Kim presenting at the EDAPS >
The award-winning paper, titled “Design and Analysis of Twin Tower High Bandwidth Memory (HBM) Architecture for Large Memory Capacity and High Bandwidth System,” was authored by mater’s student Taesoo Kim as the first author.
This paper received high acclaim for its creativity, completeness and future scalability. In particular, the innovative concept of implementing the “Twin Tower” structure to effectively address the limitations of traditional memory designs, and the ability to present a new direction in memory architecture for supporting ultra-large AI models, were recognized and led to the prestigious Best Paper Award.
< Professor Euijong Whang Elected as a New Y-KAST Member >
Professor Euijong Whang from our department has been elected as a member of the Young Korean Academy of Science and Technology (Y-KAST) of the Korean Academy of Science and Technology (KAST) for 2025.
Launched in February 2017, Y-KAST is the only young academy in Korea, consisting of outstanding young scientists under the age of 45 who engage in policy activities and international exchanges.
Y-KAST members are selected from young scientists under the age of 43 who have demonstrated outstanding academic achievements. In particular, the selection process focuses on achievements made as independent researchers in Korea after obtaining a Ph.D., ultimately choosing next-generation science and technology leaders with the potential to contribute significantly to the advancement of science and technology in Korea.
<Prof. Euijong Whang (third from left) attending the Y-KAST Member’s Day event held on December 19.>
Professor Euijong Whang has been recognized as a young scientist conducting pioneering research in the fields of big data and artificial intelligence (AI). He has led efforts in the area of data-driven responsible AI research, collaborated with global IT companies, and became the first in Asia to receive the Google AI Award. His outstanding achievements on the global stage led to his selection as a Y-KAST member in the engineering division.
With this, our department now proudly counts a total of five current Y-KAST members, including Professors Euijong Whang, Hyunjoo Lee, Junil Choi, Minsoo Rhu, and Min Seok Jang. Additionally, two alumni, Professors Joonwoo Bae and Changho Suh, have previously served as Y-KAST members.
<(From the left) Professors Kyung Cheol Choi and Jun Kyun Choi>
The research achievements of Professors Kyung Cheol Choi and Jun Kyun Choi from our department have been selected for the ‘2024 National R&D Excellence 100,’ organized by the Ministry of Science and ICT.
The National R&D Excellence 100 is a program established to enhance public understanding and interest in the role of science and technology in driving national development and to instill pride among scientists and engineers. Since 2006, outstanding national R&D achievements have been selected across ministries.
This year, a total of 869 achievements recommended by ministries, agencies, and offices were nominated. Following evaluations by a selection committee consisting of 100 industry-academic-research experts and public verification, the final 100 outstanding achievements were chosen.
<Fiber OLED that stably emits light under bending conditions >
In the field of Information/Electronics, Professor Kyung Cheol Choi’s achievement, ‘Development of the World’s Longest-Lifespan Fiber-Based OLED for Wearable Displays,’ was recognized. This technology was designed to maximize user comfort and convenience by creating fiber-type displays.
The fiber organic light-emitting diode (OLED) developed by Professor Kyung Cheol Choi is designed to operate on a single cylindrical thread. It can be produced using existing thermal deposition equipment employed in current industries, enhancing its industrial applicability and compatibility.
Notably, the fiber OLED operates stably for up to 720 hours, which is nine times longer than the previously reported maximum lifespan of 80 hours. This achievement is recognized as the highest-performing technology globally.
The light-emitting device implemented on a single thread, along with the wearable display that will be developed based on it, contributes not only to the fiberization of light-emitting devices but also sensors, batteries, and various electronic components. This core technology is expected to drive the development of diverse wearable electronic textiles. It is anticipated to spark innovation in medical and safety industries through wearable clothing-type displays and to create ripple effects across various scientific and industrial fields.
< ITU-T International Standard Adoption >
Another outstanding achievement in the Information/Electronics category is Professor Jun Kyun Choi’s ‘Development of IoT Trust Enabler Technology and Leadership in International Standards.’ This technology was developed to establish a reliable and secure intelligent IoT ecosystem.
The trust modeling algorithm developed by Professor Jun Kyun Choi for building IoT ecosystems secured approval for three international standards (Y.3057, Y.3058, Y.3060) related to IoT data trust frameworks and trust-based service delivery structures at ITU-T, the top international organization in the field of information and communication technology.
Of the 49 international standard contributions submitted, 38 were adopted, demonstrating a high adoption rate and highlighting his leadership in global standardization.
To support these standardization efforts, the trust analysis and IoT device operation technologies developed were published in 17 papers, including more than 10 in top-tier SCI international journals. Additionally, nine domestic and international patents were filed/registered, showcasing the innovation and practicality of the technology.
<(from left to right) Ph.D. candidates Song-I Cheon, Haidam Choi and Professors Minkyu Je >
The growing interest in wearable medical devices, which monitor physiological signals to analyze users’ health and predict potential diseases, has fueled advancements in various measurement technologies. One notable example is bio-impedance measurement, widely recognized for providing body composition data through “InBody.” With significant improvements in resolution, this technology can also capture plethysmography, enabling the measurement of heart rate information and further expanding its applications in health monitoring.
Recently, an international research team developed a new method to measure bio-impedance with five times greater resolution than existing technologies, using only two electrodes. This breakthrough, especially significant for the miniaturization of wearable devices, was the result of a collaboration between KAIST’s IMPACT Lab, led by Associate Professor Minkyu Je, and New York University Abu Dhabi (NYUAD), led by Associate Professor Sohmyung Ha.
Compared to the conventional four-electrode system, which is less suitable for compact devices, the two-electrode system offers significant advantages in miniaturization. However, previous two-electrode systems have faced challenges due to baseline impedance interference and increased noise proportional to the measured impedance.
Figure 1. (Left) An example of bio-impedance measurement using wearable devices; (Right) A conceptual diagram of the new impedance measurement circuit featuring baseline impedance cancellation and noise reduction functionality.
To overcome these limitations, the team developed an innovative semiconductor circuit design that effectively cancels out baseline impedance and associated noise. This design eliminates the need for a separate current generation circuit, reducing power consumption and improving measurement efficiency. The proposed system resolves noise issues caused by impedance phase and magnitude variations, achieving both high resolution and reliability.
“This bio-impedance measurement technology demonstrated up to five times better noise performance compared to conventional methods across various impedance models,” said Associate Professor Minkyu Je, a corresponding author of the work. “We believe this advancement will significantly contribute to the development of personalized health management and disease prediction technologies.”
The results of this work were published in the IEEE Journal of Solid-State Circuits, one of the most prestigious journals in the field of semiconductor integrated circuits and systems. The article, titled “A Bio-Impedance Readout IC With Complex-Domain Noise-Correlated Baseline Cancellation”, was featured in the journal in November 2024.
< Figure 2. Noise performance measurement results for various impedance models >
KAIST Ph.D. candidates Haidam Choi and Song-I Cheon were the co-first authors, while Professors Minkyu Je and Sohmyung Ha served as co-corresponding authors. The research was also presented at the International Solid-State Circuits Conference (ISSCC), the leading global conference in the field.
This work was funded by Korea’s Ministry of Science and ICT as part of projects focusing on continuous musculoskeletal monitoring and rehabilitation technologies, as well as the development of biosignal sensor-based exoskeleton devices and integrated systems.
Research Publication: IEEE Journal of Solid-State Circuits (2024), DOI:10.1109/JSSC.2024.3439865 Title: A Bio-Impedance Readout IC With Complex-Domain Noise-Correlated Baseline Cancellation
Professor Hye Won Chung has been selected as a Distinguished Lecturer by the IEEE Information Theory Society (ITSOC).
The IEEE Information Theory Society is the largest and most prestigious organization in the field of information theory. Each year, it selects 5 leading researchers as Distinguished Lecturers, offering them the opportunity to deliver invited lectures across approximately 50 chapters worldwide for two years. This program allows society members to learn about the latest research trends and outstanding achievements while engaging directly with the Distinguished Lecturers.
<An image representing graph matching research, which evaluates the similarity between two anonymized graphs, identifies one-to-one node correspondences, and expresses correlations between networks.>
Professor Hye Won Chung was recognized for her exceptional contributions to the fields of data science theory and data-efficient machine learning. She will serve as a Distinguished Lecturer from 2025 to 2026.
Furthermore, she has been invited to deliver a tutorial lecture titled “Graph Matching: Fundamental Limits and Efficient Algorithms” at the IEEE International Symposium on Information Theory (ISIT) 2024, the premier conference in information theory.
<Prof. John Kim>
