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Ferroelectric materials are being highlighted as a key material for the development of next-generation semiconductor technologies due to their characteristic of storing charges well, making them comparable to a “material that remembers electricity.” The KAIST research team has succeeded in developing high-performance, high-density next-generation memory devices that overcome the limitations of DRAM and NAND Flash memory, the two pillars of the current memory semiconductor industry.

 

EE Professor Sanghun Jeon’s research team has developed next-generation memory and storage memory technology using hafnia-based ferroelectric materials*. *Hafnia-Based Ferroelectric Material: A non-volatile insulating material actively researched as a core material for next-generation semiconductors, with excellent physical properties such as compatibility with CMOS processes, high speed, and durability.

 

DRAM memory is a type of volatile memory used to store data in devices such as smartphones, computers, and USB drives. Because of its volatile nature, stored data is lost when external power is cut off. However, it has been used as the main memory due to its low manufacturing cost and high integration density. Despite these advantages, as DRAM memory technology advances, the size of memory cells becomes smaller, reducing the capacity of the storage capacitors that store information. This eventually makes it difficult to sustain memory operation.

 

The research team focused on overcoming the limitations of these storage capacitors to achieve higher storage capacity in physically small areas. To this end, they developed a hafnia-based ferroelectric ultrathin high-k material. The results showed the lowest reported equivalent oxide thickness (EOT) of 2.4 Å (approximately one ten-thousandth the thickness of a human hair) for DRAM capacitors to date.

 

The team also developed ferroelectric memory (FRAM), which is being considered as a potential replacement for DRAM. This technology ensures non-volatile data storage and erasure even at low voltages below 1V, significantly improving energy efficiency and making it essential for next-generation memory.

 

Following advancements in DRAM technology, the team developed next-generation memory technology to overcome the limitations of NAND Flash memory using hafnia-based ferroelectric materials. NAND Flash memory, a non-volatile memory used in devices like smartphones, computers, and USB drives, has evolved to increase storage capacity by stacking multiple layers. However, physical limitations make it challenging to stack more than 500 or 1,000 layers.

 

 

In response, the research team applied ferroelectric materials to NAND Flash memory, adding a thin TiO2 interfacial layer to achieve stable data retention in a 3D vertical structure with over 1,000 layers. Furthermore, the team succeeded in developing a high-performance oxide channel-based NAND Flash device, capable of storing more data and maintaining data stability for over 10 years, overcoming the limitations of traditional oxide channel-based memory devices that struggled with complete data erasure.

 

Professor Jeon stated, “These research results are expected to provide a breakthrough in memory semiconductor technology, which has been stagnant due to scaling issues, and contribute to the commercialization of various AI computing and edge computing technologies in the future.”

 

 

Dr. Venkateswarlu Gaddam, PhD candidates Ki-Wook Kim, Hong-Rae Cho, Jung-Hyun Hwang, Sang-Ho Lee, master’s students Hyo-Jun Choi and Hyun-Jun Kang participated as co-first authors. These research achievements were internationally recognized, with five papers presented at top-tier semiconductor industry conferences in 2024 (2 at VLSI 2024, 3 at IEDM 2024).

 

• “In-depth analysis of the Hafnia ferroelectrics as a key enabler for low voltage & QLC 3D VNAND beyond 1K layers: Experimental demonstration and modeling,” VLSI 2024. DOI: 10.1109/VLSITechnologyandCir46783.2024

 

• “Low-Damage Processed and High-Pressure Annealed High-k Hafnium Zirconium Oxide Capacitors near Morphotropic Phase Boundary with Record-Low EOT of 2.4 Å & high-k of 70 for DRAM,” VLSI 2024. DOI: 10.1109/VLSITechnologyandCir46783.2024

 

• “Unveiling the Origin of Disturbance in FeFET and the Potential of Multifunctional TiO2 as a Breakthrough for Disturb-free 3D NAND Cell: Experimental and Modeling,” IEDM 2024.

 

• “Oxide Channel Ferroelectric NAND Device with Source-Tied Covering Metal Structure: Wide Memory Window (14.3 V), Reliable Retention (> 10 years) and Disturbance Immunity (△Vth ≤ 0.1 V) for QLC Operation,” IEDM 2024.

 

• “Design Methodology for Low-Voltage Operational (≤1 V) FRAM Cell Capacitors and Approaches for Overcoming Disturb Issues in 1T-nC Arrays: Experimental & Modeling,” IEDM 2024.
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IEEE VLSI and IEEE IEDM conferences are considered the “Olympics of semiconductors,” where leading companies like Samsung Electronics, SK Hynix, Micron, and Intel, as well as renowned academics, share the latest technological advancements and discuss future directions.

 

This research was conducted in collaboration with Samsung Electronics and Hanyang University, supported by the Korea Evaluation Institute of Industrial Technology (KEIT), the Ministry of Science and ICT’s Innovation Research Center (IRC) program, and funding from Samsung Electronics.

 

Professor Minkyu Je from our department was recognized for his contributions to the advancement of the AI semiconductor industry through the development of innovative neural network computation circuits and system technologies based on embedded Magnetoresistive Random Access Memory (eMRAM) Process-In-Memory (PIM) technology. He was awarded a commendation from the Ministry of Science and ICT at the Future Technology Conference on AI Semiconductors held on December 20.

 

Since April 1, 2022, Professor Je’s research team at the Integrated Memory & Processor Architecture for Compact Systems (IMPACT) Lab has been working on the “Development of Core Technologies for High-Efficiency AI Semiconductors Utilizing eMRAM-based PIM Technology” project, supported by the Ministry of Science and ICT and supervised by the Institute for Information & communication Technology Planning & evaluation. Through this project, the team has achieved remarkable results. These include the development of neural network computation circuit technology that consumes low power, allows for adjustable computational precision, and improves memory utilization efficiency by more than twofold compared to existing technologies. They also developed a weight representation method and supporting circuit architecture that reduce computational errors caused by analog variations during in-memory analog computation, while simultaneously reducing power consumption. Furthermore, they introduced an efficient analog neural network accelerator technology capable of processing the entire neural network computation within a PIM-based System-on-Chip (SoC). This technology is robust against computational errors due to analog variations and can be applied to large-scale neural network models without retraining.

 

Master’s candidate Taesoo Kim from Professor Jeongho Kim’s lab achieved remarkable success by winning the Best Paper Award at the ‘IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) 2024‘, held on December 17-19 at the Taj Yeshwantpur, in Bangalore, India.

 

The ‘IEEE EDAPS’ is the largest and most influential conference on semiconductor packaging technology in the Asia-Pacific region. Since 2002, it has been annually organized and hosted by the IEEE Electronic Packaging Society. 

 

 

The award-winning paper, titled “Design and Analysis of Twin Tower High Bandwidth Memory (HBM) Architecture for Large Memory Capacity and High Bandwidth System,” was authored by mater’s student Taesoo Kim as the first author. 

 

This paper received high acclaim for its creativity, completeness and future scalability. In particular, the innovative concept of implementing the “Twin Tower” structure to effectively address the limitations of traditional memory designs, and the ability to present a new direction in memory architecture for supporting ultra-large AI models, were recognized and led to the prestigious Best Paper Award.

 

The growing interest in wearable medical devices, which monitor physiological signals to analyze users’ health and predict potential diseases, has fueled advancements in various measurement technologies. One notable example is bio-impedance measurement, widely recognized for providing body composition data through “InBody.” With significant improvements in resolution, this technology can also capture plethysmography, enabling the measurement of heart rate information and further expanding its applications in health monitoring.

 

Recently, an international research team developed a new method to measure bio-impedance with five times greater resolution than existing technologies, using only two electrodes. This breakthrough, especially significant for the miniaturization of wearable devices, was the result of a collaboration between KAIST’s IMPACT Lab, led by Associate Professor Minkyu Je, and New York University Abu Dhabi (NYUAD), led by Associate Professor Sohmyung Ha.

 

Compared to the conventional four-electrode system, which is less suitable for compact devices, the two-electrode system offers significant advantages in miniaturization. However, previous two-electrode systems have faced challenges due to baseline impedance interference and increased noise proportional to the measured impedance.

 

To overcome these limitations, the team developed an innovative semiconductor circuit design that effectively cancels out baseline impedance and associated noise. This design eliminates the need for a separate current generation circuit, reducing power consumption and improving measurement efficiency. The proposed system resolves noise issues caused by impedance phase and magnitude variations, achieving both high resolution and reliability.

 

“This bio-impedance measurement technology demonstrated up to five times better noise performance compared to conventional methods across various impedance models,” said Associate Professor Minkyu Je, a corresponding author of the work. “We believe this advancement will significantly contribute to the development of personalized health management and disease prediction technologies.”

 

The results of this work were published in the IEEE Journal of Solid-State Circuits, one of the most prestigious journals in the field of semiconductor integrated circuits and systems. The article, titled “A Bio-Impedance Readout IC With Complex-Domain Noise-Correlated Baseline Cancellation”, was featured in the journal in November 2024.

 

 

KAIST Ph.D. candidates Haidam Choi and Song-I Cheon were the co-first authors, while Professors Minkyu Je and Sohmyung Ha served as co-corresponding authors. The research was also presented at the International Solid-State Circuits Conference (ISSCC), the leading global conference in the field.

 

This work was funded by Korea’s Ministry of Science and ICT as part of projects focusing on continuous musculoskeletal monitoring and rehabilitation technologies, as well as the development of biosignal sensor-based exoskeleton devices and integrated systems.

 

Research Publication:
IEEE Journal of Solid-State Circuits (2024), DOI:10.1109/JSSC.2024.3439865
Title: A Bio-Impedance Readout IC With Complex-Domain Noise-Correlated Baseline Cancellation

Master’s candidate Woo-Hyun Hwang and undergraduate student Jae-Jun Lee from Professor Seonghwan Cho’s lab achieved remarkable success by winning the Grand Prize at the ‘2024 Korean University Semiconductor Circuit Design Competition Award Ceremony’, held on December 11 at the Grand InterContinental Seoul Parnas Hotel.

 

The ‘Korean University Semiconductor Circuit Design Competition’, organized by the Institute of Semiconductor Engineers, aims to nurture IC circuit design skills among university students nationwide, discover creative ideas, and is supported by numerous semiconductor-related companies.

 

 

At the awards ceremony on December 11, the Grand Prize-winning project titled ‘A Chip-Scale Operable Magnetic Resonance-Based Two-Coil Wireless Communication System’ was developed by Woo-Hyun Hwang and Jae-Jun Lee.

 

The project received high praise for its creativity, complexity, and level of completion. In particular, the innovative concept of implementing a “magnetic resonance-based two-coil system” at a chip scale, and the ability to achieve effective design with high completion in challenging wireless communication environments, were recognized and led to the Grand Prize award.