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(October 6) Digital Neuromorphic Processor Design with Large Fan-in/out On-Chip Learning


Digital Neuromorphic Processor Design with Large Fan-in/out On-Chip Learning


Tuesday, October 6th, 2015 - 1:00 ~ 2:30 pm


Jae-sun Seo (Professor, Arizona State University)


Wooribyul Seminar Room (E3 #2201)


In recent years, both industry and academia have shown keen interest in neuromorphic computing and its hardware design for cognitive applications. Although off-chip training is commonly performed, on-chip learning is crucial to accelerate training or continuously adapt with real-time sensory input. As an exemplary work, a 65nm neuromorphic processor that performs on-line spike-clustering for deep-brain sensing applications is implemented. The processor exhibits superior sorting accuracy with a footprint of 0.25mm2/ch and a power consumption of 9.3µW/ch at 0.3V supply. Proceeding towards large scale systems that can learn and classify on-chip, we propose neuromorphic architecture and circuits that can support various STDP (spike-timing dependent plasticity) learning rules and various types of inhibition (lateral, feed-forward) with large (1,000) fan-in/out per neuron. Preliminary implementation results of the proposed core in 65nm CMOS will be discussed.


Jae-sun Seo received his Ph.D. degree from the University of Michigan in 2010 in electrical engineering. From 2010 to 2013, he was with IBM T. J. Watson Research Center, where he worked on energy-efficient circuits for high-performance processors and neuromorphic chip design for the DARPA SyNAPSE project. In January 2014, he joined Arizona State University as an assistant professor in the School of ECEE. During the summer of 2015, he was a visiting faculty at Intel Circuit Research Labs. His research interests include efficient hardware design of learning algorithms and integrated power management. He received the IBM outstanding technical achievement award in 2012, and serves on the technical program committee for ISLPED.