세미나

In recent years, both industry and academia have shown keen interest in neuromorphic computing and its hardware design for cognitive applications. Although off-chip training is commonly performed, on-chip learning is crucial to accelerate training or continuously adapt with real-time sensory input. As an exemplary work, a 65nm neuromorphic processor that performs on-line spike-clustering for deep-brain sensing applications is implemented. The processor exhibits superior sorting accuracy with a footprint of 0.25mm2/ch and a power consumption of 9.3µW/ch at 0.3V supply. Proceeding towards large scale systems that can learn and classify on-chip, we propose neuromorphic architecture and circuits that can support various STDP (spike-timing dependent plasticity) learning rules and various types of inhibition (lateral, feed-forward) with large (1,000) fan-in/out per neuron. Preliminary implementation results of the proposed core in 65nm CMOS will be discussed.