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School of Electrical Engineering We thrive
to be the world’s
top IT powerhouse.
We thrive to be the world’s top IT powerhouse.

Our mission is to lead innovations
in information technology, create lasting impact,
and educate next-generation leaders of the world.

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School of Electrical Engineering We thrive
to be the world’s
top IT powerhouse.
We thrive to be the world’s top IT powerhouse.

Our mission is to lead innovations
in information technology, create lasting impact,
and educate next-generation leaders of the world.

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  • 6
Learn More
School of Electrical Engineering We thrive
to be the world’s
top IT powerhouse.
We thrive to be the world’s top IT powerhouse.

Our mission is to lead innovations
in information technology, create lasting impact,
and educate next-generation leaders of the world.

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  • 6
Learn More
School of Electrical Engineering We thrive
to be the world’s
top IT powerhouse.
We thrive to be the world’s top IT powerhouse.

Our mission is to lead innovations
in information technology, create lasting impact,
and educate next-generation leaders of the world.

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  • 6
Learn More
School of Electrical Engineering We thrive
to be the world’s
top IT powerhouse.
We thrive to be the world’s top IT powerhouse.

Our mission is to lead innovations
in information technology, create lasting impact,
and educate next-generation leaders of the world.

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AI in EE AI and machine learning
are a key thrust
in EE research
AI and machine learning are a key thrust in EE research

AI/machine learning  efforts are already   a big part of   ongoing
research in all 6 divisions - Computer, Communication, Signal,
Wave, Circuit and Device - of KAIST EE 

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Highlights

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Professor Chan-Hyun Youn’s Research Team Developed a Technique to Prevent Abnormal Data Generation in Diffusion Models

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<(From left) Professor Chan-Hyun Youn, Jinhyeok Jang Ph.D. candidate, Changha Lee Ph.D. candidate, Minsu Jeon Ph.D. >

 

Professor Chan-Hyun Youn’s research team from the EE department has developed a momentum-based generation technique to address the issue of abnormal data generation frequently encountered by diffusion model-based generative AI.

While diffusion model-based generative AI, which has recently garnered significant attention, generally produces realistic images, it often generates abnormal details, such as unnaturally bent joints or horses with only three legs.

 

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Figure 1 : The generated images by Stable Diffusion with the proposed technique

 

To address this problem, the research team reformulated the generative process of diffusion models as an optimization problem, such as gradient descent. Both the generative process of diffusion models and gradient descent can be expressed as a Generalized Expectation-Maximization problem, and visualization revealed the presence of numerous local minima and saddle points in the generative process.

This observation demonstrated that inappropriate outcomes are akin to local minima or saddle points. Based on this insight, the team introduced the widely used momentum technique from optimization into the generative process.

 

Various experiments confirmed that the generation of inappropriate images significantly decreased without additional training, and the quality of generated images improved even with reduced computational cost. These results suggest a new insight about the generative process of diffusion models as a progressive optimization problem and show that introducing the momentum technique into the generative process reduces inappropriate outcomes.

 

This new research outcome is expected to not only improve generation results but also provide a new interpretation of generative AI and inspire various follow-up studies. The research findings were presented in February at the 38th Annual AAAI Conference on Artificial Intelligence (AAAI 2024) in Vancouver, Canada, one of the leading international conferences in the AI field, under the title “Rethinking Peculiar Images by Diffusion Models: Revealing Local Minima’s Role.”

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Professor Chan-Hyun Youn’s Research Team Developed a Dataset Watermarking Technique for Dataset Copyright Protection

3844433368535702746.3844433844043905195@dooray3844433368535702746.3844433844073238403@dooray

<Professor Chan-Hyun Youn, and Jinhyeok Jang Ph.D. candidate>

 

Professor Chan-Hyun Youn’s research team from the EE department has developed a technique for dataset copyright protection named “Undercover Bias.” Undercover Bias is based on the premise that all datasets contain bias and that bias itself has discriminability. By embedding artificially generated biases into a dataset, it is possible to verify AI models using the watermarked data without adequate permission.

 

This technique addresses the issues of data copyright and privacy protection, which have become significant societal concerns with the rise of AI. It embeds a very subtle watermark into the target dataset. Unlike prior methods, the watermark is nearly imperceptible and clean-labeled. However, AI models trained on the watermarked dataset unintentionally acquire the ability to classify the watermark. The presence or absence of this property allows for the verification of unauthorized use of the dataset.

 

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Figure 1 : Schematic of verification based on Undercover Bias

 

The research team demonstrated that the proposed method can verify models trained using the watermarked dataset with 100% accuracy across various benchmarks.

Further, they showed that models trained with adequate permission are misidentified as unauthorized with a probability of less than 3e-5%, proving the high reliability of the proposed watermark. The study will be presented at one of the leading international conferences in the field of computer vision, the European Conference on Computer Vision (ECCV) 2024, to be held in Milan, Italy, in October this year.

 

ECCV is renowned in the field of computer vision, alongside conferences like CVPR and ICCV, as one of the top-tier international academic conferences. The paper will be titled “Rethinking Data Bias: Dataset Copyright Protection via Embedding Class-wise Hidden Bias.”

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Professor Chan-Hyun Youn’s Research Team Developed a Network Calibration Technique to Improve the reliability of artificial neural networks

3844424708055224837.3844427238256168274@dooray3844424708055224837.3844427238272435522@dooray

<(from left) Professor Chan-Hyun Youn, Gyusang Cho ph.d. candidate>

 

Professor Chan-Hyun Youn’s research team from the EE department, has successfully developed a network calibration algorithm called “Tilt and Average; TNA” to improve the reliability of neural networks. Unlike existing methods based on calibration maps, the TNA technique transforms the weights of the classifier’s last layer, offering a significant advantage in that it can be seamlessly integrated with existing methods. This research is being evaluated as an outstanding technology in the field of enhancing artificial intelligence reliability.

3844424708055224837.3844427238236031186@dooray

 

The research proposes a new algorithm to address the overconfident prediction problem inherent in existing artificial neural networks. Utilizing the high-dimensional geometry of the last linear layer, this algorithm focuses on the angular aspects between the row vectors of the weights, suggesting a mechanism to adjust (Tilt) and compute the average (Average) of their directions.

 

The research team confirmed that the proposed method can reduce calibration error by up to 20%, and the algorithm’s ability to integrate with existing calibration map-based techniques is a significant advantage. The results of this study are scheduled to be presented at the ICML (International Conference on Machine Learning, https://icml.cc), one of the premier international conferences in the field of artificial intelligence, held in Vienna, Austria, this July. Now in its 41st year, ICML is renowned as one of the most prestigious and long-standing international conferences in the machine learning field, alongside other top conferences such as CVPR, ICLR, and NeurIPS.

 

In addition, this research was conducted with support from the Korea Coast Guard (RS-2023-00238652) and the Defense Acquisition Program Administration (DAPA) (KRIT-CT-23-020). The paper can be found as : Gyusang Cho and Chan-Hyun Youn, “Tilt and Average : Geometric Adjustment of the Last Layer for Recalibration”, ICML (2024) 

 
Professor Changick Kim’s Research Team Develops ‘VideoMamba,’ a High-Efficiency Model Opening a New Paradigm in Video Recognition

1

<(From left) Professor Changick Kim, Jinyoung Park integrated Ph.D. candidate, Hee-Seon Kim Ph.D. candidate, Kangwook Ko Ph.D. candidate, and Minbeom Kim Ph.D. candidate>

 

On the 9th, Professor Changick Kim’s research team announced the development of a high-efficiency video recognition model named ‘VideoMamba.’ VideoMamba demonstrates superior efficiency and competitive performance compared to existing video models built on transformers, like those underpinning large language models such as ChatGPT. This breakthrough is seen as pioneering a new paradigm in the field of video utilization.

 

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Figure 1: Comparison of VideoMamba’s memory usage and inference speed with transformer-based video recognition models. 

VideoMamba is designed to address the high computational complexity associated with traditional transformer-based models. These models typically rely on the self-attention mechanism, which scales quadratically in complexity. However, VideoMamba utilizes a Selective State Space Model (SSM) mechanism, enabling efficient linear complexity processing. This allows VideoMamba to effectively capture the spatio-temporal information in videos and efficiently handle long dependencies within video data.

 

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Figure 2: Detailed structure of the spatio-temporal forward and backward Selective State Space Model in VideoMamba. 

 

To maximize the efficiency of the video recognition model, Professor Kim’s team incorporated spatio-temporal forward and backward SSMs into VideoMamba. This model integrates non-sequential spatial information and sequential temporal information effectively, enhancing video recognition performance. The research team validated VideoMamba’s performance across various video recognition benchmarks.

As a result, VideoMamba achieved high accuracy with low GFLOPs (Giga Floating Point Operations) and memory usage, and it demonstrated very fast inference speed.

 

VideoMamba offers an efficient and practical solution for various applications requiring video analysis. For example, autonomous driving can analyze driving footage to accurately assess road conditions and recognize pedestrians and obstacles in real time, thereby preventing accidents. In the medical field, it can analyze surgical videos to monitor the patient’s condition in real-time and respond swiftly to emergencies.

In sports, it can analyze players’ movements and tactics during games to improve strategies and detect fatigue or potential injuries during training to prevent them. VideoMamba’s fast processing speed, low memory usage, and high performance provide significant advantages in these diverse video utilization fields.

 

The research team includes Jinyoung Park (integrated Ph.D candidate), Hee-Seon Kim (Ph.D. candidate), Kangwook Ko (Ph.D. candidate) as co-first authors, and Minbeom Kim (Ph.D. candidate) as a co-author, with Professor Changick Kim as the corresponding author from the Department of Electrical and Electronic Engineering at KAIST.

The research findings will be presented at the European Conference on Computer Vision (ECCV) 2024, one of the top international conferences in the field of computer vision, to be held in Milan, Italy, in September this year. (Paper title: VideoMamba: Spatio-Temporal Selective State Space Model).

 

This work was supported by the Institute of Information & communications Technology Planning & Evaluation (IITP) grant funded by the Korea government (MSIT) (No.2020-0-00153, Penetration Security Testing of ML Model Vulnerabilities and Defense).

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[Professor Myoungsoo Jung’s Research Team Pioneers the ‘CXL-GPU’ Market. KAIST Develops High Capacity and Performance GPU]
 
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<Professor Myoungsoo Jung’s Research Team>
 

Recently, big tech companies at the forefront of large-scale AI service provision are competitively increasing the size of their models and data to deliver better performance to users. The latest large-scale language models require tens of terabytes (TB, 10^12 bytes) of memory for training. A domestic research team has developed a next-generation interface technology-enabled high-capacity, high-performance AI accelerator that can compete with NVIDIA, which currently dominates the AI accelerator market.

 

Professor Jung Myoungsoo’s research team, announced on the 8th that they have developed a technology to optimize the memory read/write performance of high-capacity GPU devices with the next-generation interface technology, Compute Express Link (CXL).

 

The internal memory capacity of the latest GPUs is only a few tens of gigabytes (GB, 10^9 bytes), making it impossible to train and infer models with a single GPU. To provide the memory capacity required by large-scale AI models, the industry generally adopts the method of connecting multiple GPUs. However, this method significantly increases the total cost of ownership (TCO) due to the high prices of the latest GPUs.

 

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< Representative Image of the CXL-GPU >

 

Therefore, the ‘CXL-GPU’ structure technology, which directly connects large-capacity memory to GPU devices using the next-generation connection technology, CXL, is being actively reviewed in various industries. However, the high-capacity feature of CXL-GPU alone is not sufficient for practical AI service use. Since large-scale AI services require fast inference and training performance, the memory read/write performance to the memory expansion device directly connected to the GPU must be comparable to that of the local memory of the existing GPU for actual service utilization.

 

*CXL-GPU: It supports high capacity by integrating the memory space of memory expansion devices connected via CXL into the GPU memory space. The CXL controller automatically handles operations needed for managing the integrated memory space, allowing the GPU to access the expanded memory space in the same manner as accessing its local memory. Unlike the traditional method of purchasing additional expensive GPUs to increase memory capacity, CXL-GPU can selectively add memory resources to the GPU, significantly reducing system construction costs.

 

Our research team has developed technology to improve the causes of decreased memory read/write performance of CXL-GPU devices. By developing technology that allows the memory expansion device to determine its memory write timing independently, the GPU device can perform memory writes to the memory expansion device and the GPU’s local memory simultaneously. This means that the GPU does not have to wait for the completion of the memory write task, thereby solving the write performance degradation issue.

 

제안하는 CXL-GPU의 구조

< Proposed CXL-GPU Architecture > 

 

Furthermore, the research team developed a technology that provides hints from the GPU device side to enable the memory expansion device to perform memory reads in advance.

Utilizing this technology allows the memory expansion device to start memory reads faster, achieving faster memory read performance by reading data from the cache (a small but fast temporary data storage space) when the GPU device actually needs the data.

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< CXL-GPU Hardware Prototype >

 

This research was conducted using the ultra-fast CXL controller and CXL-GPU prototype from Panmnesia*, a semiconductor fabless startup. Through the technology efficacy verification using Panmnesia’s CXL-GPU prototype, the research team confirmed that it could execute AI services 2.36 times faster than existing GPU memory expansion technology. The results of this research will be presented at the USENIX Association Conference and HotStorage research presentation in Santa Clara this July.

 

*Panmnesia possesses a proprietary CXL controller with pure domestic technology that has reduced the round-trip latency for CXL memory management operations to less than double-digit nanoseconds (nanosecond, 10^9 of a second) for the first time in the industry. This is more than three times faster than the latest CXL controllers worldwide. Panmnesia has utilized its high-speed CXL controller to directly connect multiple memory expansion devices to the GPU, enabling a single GPU to form a large-scale memory space in the terabyte range.

Professor Jung stated, “Accelerating the market adoption of CXL-GPU can significantly reduce the memory expansion costs for big tech companies operating large-scale AI services.”

 

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< Evaluation Results of CXL-GPU Execution Time > 

 
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Professor Chan-Hyun Youn Signs MOU to Establish a Graduate Program in Satellite System Technology with Vietnam’s Hanoi University of Science and Technology and Daejeon-based Satellite Specialist Companies

 

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<(from left) Professor Chan-Hyun Youn, Young Wook Kim CEO(IOPS), So Young Kim Vice President, Nguyen Phong Dien Vice President(HUST), Hoang Si Hong Vice Dean(HUST),          Myung Jin Choi CEO(HANCOM InSpace) Truong Thu Huong(HUST)>
 
 
Professor Chan-Hyun Youn is advancing a collaboration with Vietnam’s Hanoi University of Science and Technology (HUST) and specialized satellite communication and service companies in Daejeon to establish a graduate program focused on satellite systems and application technologies.
 
This collaboration aims to enhance expertise in various fields such as ocean monitoring and climate change response using satellite systems and data, promoting research and educational cooperation between Korean and Vietnamese universities. Specifically, KAIST aims to strengthen industry-academia cooperation related to future satellite systems and service technologies between Korea and Vietnam, based on the satellite application technology jointly researched by KAIST and led by the Korea Aerospace Research Institute.
 
To achieve this, KAIST and HUST have agreed to pursue educational and research cooperation in satellite systems and application technologies and have signed a Memorandum of Understanding (MoU) to establish a specialized graduate program in satellite system technology at KAIST. The School of Electrical Engineering at KAIST (KAIST-EE) and the School of Electrical Engineering at HUST (HUST-SEEE) will closely cooperate on detailed educational content, including curriculum development and student exchanges.
 
KAIST has also separately signed MoU to support the establishment of the ‘Graduate Program in Satellite System Technology (GST)’ with HUST and venture companies such as I-OPS Co., Ltd. (CEO: Youngwook Kim) and Hancom InSpace Co., Ltd. (CEO: Myungjin Choi).
 
I-OPS Co., Ltd. and Hancom InSpace Co., Ltd., specialized satellite technology companies based in Daejeon, which is becoming the hub of space and satellite technology in the NewSpace era, will support technological cooperation and the nurturing of outstanding talents from HUST. Furthermore, they plan to collaborate with Viettel, Vietnam’s state-owned communication system and service company, on satellite technology and application services, jointly with HUST.
 
Professor Chan-Hyun Youn stated that this collaboration aims to enhance the global business competitiveness of the domestic satellite industry by advancing the development and operational capabilities of next-generation satellite systems. He emphasized that the theoretical and advanced expertise accumulated by the School of Electrical Engineering at KAIST in core satellite technologies, such as satellite onboard computing, sensing, communication and antenna, and signal processing, combined with the integrative education and research and development capabilities, will mutually benefit from the collaboration with domestic satellite-related companies.
 
This collaboration is expected to contribute to the development and global competitiveness of the space industry in both Korea and Vietnam through the establishment of a global satellite education network between the academic and industrial sectors of both countries.
 

 

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Professor Minsoo Rhu has been inducted into the Hall of Fame of the IEEE/ACM International Symposium on Computer Architecture (ISCA) 2024

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<Professor Minsoo Rhu>
 
Professor Minsoo Rhu has been inducted into the Hall of Fame of the IEEE/ACM International Symposium on Computer Architecture (ISCA) this year.
 
ISCA (https://www.iscaconf.org/isca2024/) is an international conference with a long history (51th year) and the highest authority in the field of computer architecture. Along with the MICRO (IEEE/ACM International Symposium on Microarchitecture) and HPCA (IEEE International Symposium on High-Performance Computer Architecture) conferences, it is considered as one of the top three international conferences in the computer architecture field.
 
Professor Minsoo Rhu is a leading researcher in South Korea on research in AI semiconductors and GPU-based high-performance computing systems within the field of computer architecture. Following his induction into the HPCA Hall of Fame in 2021 and the MICRO Hall of Fame in 2022, he has published more than eight papers at ISCA and has been inducted into the ISCA Hall of Fame in 2024.
 
This year, the ISCA conference will be held from June 29 to July 3 in Buenos Aires, Argentina, where Professor Rhu’s research team will present a total of three papers (see below).
 
[Information on Professor Minsoo Rhu’s Research Team’s ISCA Presentations]
 
1. Yujeong Choi, Jiin Kim, and Minsoo Rhu, “ElasticRec: A Microservice-based Model Serving Architecture Enabling Elastic Resource Scaling for Recommendation Models,” ISCA-51     
 
2. Yunjae Lee, Hyeseong Kim, and Minsoo Rhu, “PreSto: An In-Storage Data Preprocessing System for Training Recommendation Models,” ISCA-51
 
3. Ranggi Hwang, Jianyu Wei, Shijie Cao, Changho Hwang, Xiaohu Tang, Ting Cao, and Mao Yang, “Pre-gated MoE: An Algorithm-System Co-Design for Fast and Scalable Mixture-of-Expert Inference,” ISCA-51 

 

Professor Kim Lee-Sup Lab’s Master’s Graduate Park Jun-Young Wins Best Paper Award at the International Design Automation Conference

 

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<(From left to right) Professor Kim Lee-Sup, Master’s Graduate Park Jun-Young, Ph.D. Graduate Kang Myeong-Goo, Master’s Graduate Kim Yang-Gon, Ph.D. Graduate Shin Jae-Kang,    Ph.D. Candidate Han Yunki>

 

Master’s graduate Park Jun-Young from Professor Kim Lee-Sup’s lab of our department achieved the significant accomplishment of winning the Best Paper Award at the International Design Automation Conference (DAC) held in San Francisco, USA, from June 23 to June 27. Established in 1964, DAC is an international academic conference in its 61st year, covering semiconductor design automation, AI algorithms, and chip design. It is considered the highest authority in the related field, with only about 20 percent of submitted papers being selected for presentation.

The awarded research is based on Park Jun-Young’s master’s thesis, proposing an algorithmic approximation technique and hardware architecture to reduce memory transfer for KV caching, a problem in Large Language Model inference. The excellence of this research was recognized by the Best Paper Award selection committee and was chosen as the final Best Paper Award winner from among the four candidate papers (out of 337 presented and 1,545 submitted papers).

The details are as follows:

 

  • Conference Name: 2024 61st IEEE/ACM Design Automation Conference (DAC)
  • Date: June 23-27, 2024
  • Award: Best Paper Award
  • Authors: Park Jun-Young, Kang Myeong-Goo, Han Yunki, Kim Yang-Gon, Shin Jae-Kang, Kim Lee-Sup (Advisor)
  • Paper Title: Token-Picker: Accelerating Attention in Text Generation with Minimized Memory Transfer via Probability Estimation

 

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