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Professor Chan-Hyun Youn’s Research Team Developed a Dataset Watermarking Technique for Dataset Copyright Protection

<Professor Chan-Hyun Youn, and Jinhyeok Jang Ph.D. candidate>

 

Professor Chan-Hyun Youn’s research team from the EE department has developed a technique for dataset copyright protection named “Undercover Bias.” Undercover Bias is based on the premise that all datasets contain bias and that bias itself has discriminability. By embedding artificially generated biases into a dataset, it is possible to verify AI models using the watermarked data without adequate permission.

 

This technique addresses the issues of data copyright and privacy protection, which have become significant societal concerns with the rise of AI. It embeds a very subtle watermark into the target dataset. Unlike prior methods, the watermark is nearly imperceptible and clean-labeled. However, AI models trained on the watermarked dataset unintentionally acquire the ability to classify the watermark. The presence or absence of this property allows for the verification of unauthorized use of the dataset.

 

Figure 1 : Schematic of verification based on Undercover Bias

 

The research team demonstrated that the proposed method can verify models trained using the watermarked dataset with 100% accuracy across various benchmarks.

Further, they showed that models trained with adequate permission are misidentified as unauthorized with a probability of less than 3e-5%, proving the high reliability of the proposed watermark. The study will be presented at one of the leading international conferences in the field of computer vision, the European Conference on Computer Vision (ECCV) 2024, to be held in Milan, Italy, in October this year.

 

ECCV is renowned in the field of computer vision, alongside conferences like CVPR and ICCV, as one of the top-tier international academic conferences. The paper will be titled “Rethinking Data Bias: Dataset Copyright Protection via Embedding Class-wise Hidden Bias.”

Professor Chan-Hyun Youn’s Research Team Developed a Network Calibration Technique to Improve the reliability of artificial neural networks

<(from left) Professor Chan-Hyun Youn, Gyusang Cho ph.d. candidate>

 

Professor Chan-Hyun Youn’s research team from the EE department, has successfully developed a network calibration algorithm called “Tilt and Average; TNA” to improve the reliability of neural networks. Unlike existing methods based on calibration maps, the TNA technique transforms the weights of the classifier’s last layer, offering a significant advantage in that it can be seamlessly integrated with existing methods. This research is being evaluated as an outstanding technology in the field of enhancing artificial intelligence reliability.

 

The research proposes a new algorithm to address the overconfident prediction problem inherent in existing artificial neural networks. Utilizing the high-dimensional geometry of the last linear layer, this algorithm focuses on the angular aspects between the row vectors of the weights, suggesting a mechanism to adjust (Tilt) and compute the average (Average) of their directions.

 

The research team confirmed that the proposed method can reduce calibration error by up to 20%, and the algorithm’s ability to integrate with existing calibration map-based techniques is a significant advantage. The results of this study are scheduled to be presented at the ICML (International Conference on Machine Learning, https://icml.cc), one of the premier international conferences in the field of artificial intelligence, held in Vienna, Austria, this July. Now in its 41st year, ICML is renowned as one of the most prestigious and long-standing international conferences in the machine learning field, alongside other top conferences such as CVPR, ICLR, and NeurIPS.

 

In addition, this research was conducted with support from the Korea Coast Guard (RS-2023-00238652) and the Defense Acquisition Program Administration (DAPA) (KRIT-CT-23-020). The paper can be found as : Gyusang Cho and Chan-Hyun Youn, “Tilt and Average : Geometric Adjustment of the Last Layer for Recalibration”, ICML (2024) 

Recently, big tech companies at the forefront of large-scale AI service provision are competitively increasing the size of their models and data to deliver better performance to users. The latest large-scale language models require tens of terabytes (TB, 10^12 bytes) of memory for training. A domestic research team has developed a next-generation interface technology-enabled high-capacity, high-performance AI accelerator that can compete with NVIDIA, which currently dominates the AI accelerator market.

 

Professor Jung Myoungsoo’s research team, announced on the 8th that they have developed a technology to optimize the memory read/write performance of high-capacity GPU devices with the next-generation interface technology, Compute Express Link (CXL).

 

The internal memory capacity of the latest GPUs is only a few tens of gigabytes (GB, 10^9 bytes), making it impossible to train and infer models with a single GPU. To provide the memory capacity required by large-scale AI models, the industry generally adopts the method of connecting multiple GPUs. However, this method significantly increases the total cost of ownership (TCO) due to the high prices of the latest GPUs.

 

< Representative Image of the CXL-GPU >

 

Therefore, the ‘CXL-GPU’ structure technology, which directly connects large-capacity memory to GPU devices using the next-generation connection technology, CXL, is being actively reviewed in various industries. However, the high-capacity feature of CXL-GPU alone is not sufficient for practical AI service use. Since large-scale AI services require fast inference and training performance, the memory read/write performance to the memory expansion device directly connected to the GPU must be comparable to that of the local memory of the existing GPU for actual service utilization.

 

*CXL-GPU: It supports high capacity by integrating the memory space of memory expansion devices connected via CXL into the GPU memory space. The CXL controller automatically handles operations needed for managing the integrated memory space, allowing the GPU to access the expanded memory space in the same manner as accessing its local memory. Unlike the traditional method of purchasing additional expensive GPUs to increase memory capacity, CXL-GPU can selectively add memory resources to the GPU, significantly reducing system construction costs.

 

Our research team has developed technology to improve the causes of decreased memory read/write performance of CXL-GPU devices. By developing technology that allows the memory expansion device to determine its memory write timing independently, the GPU device can perform memory writes to the memory expansion device and the GPU’s local memory simultaneously. This means that the GPU does not have to wait for the completion of the memory write task, thereby solving the write performance degradation issue.

 

< Proposed CXL-GPU Architecture > 

 

Furthermore, the research team developed a technology that provides hints from the GPU device side to enable the memory expansion device to perform memory reads in advance.

Utilizing this technology allows the memory expansion device to start memory reads faster, achieving faster memory read performance by reading data from the cache (a small but fast temporary data storage space) when the GPU device actually needs the data.

< CXL-GPU Hardware Prototype >

 

This research was conducted using the ultra-fast CXL controller and CXL-GPU prototype from Panmnesia*, a semiconductor fabless startup. Through the technology efficacy verification using Panmnesia’s CXL-GPU prototype, the research team confirmed that it could execute AI services 2.36 times faster than existing GPU memory expansion technology. The results of this research will be presented at the USENIX Association Conference and HotStorage research presentation in Santa Clara this July.

 

*Panmnesia possesses a proprietary CXL controller with pure domestic technology that has reduced the round-trip latency for CXL memory management operations to less than double-digit nanoseconds (nanosecond, 10^9 of a second) for the first time in the industry. This is more than three times faster than the latest CXL controllers worldwide. Panmnesia has utilized its high-speed CXL controller to directly connect multiple memory expansion devices to the GPU, enabling a single GPU to form a large-scale memory space in the terabyte range.

Professor Jung stated, “Accelerating the market adoption of CXL-GPU can significantly reduce the memory expansion costs for big tech companies operating large-scale AI services.”

 

< Evaluation Results of CXL-GPU Execution Time > 

Professor Minsoo Rhu has been inducted into the Hall of Fame of the IEEE/ACM International Symposium on Computer Architecture (ISCA) 2024

 

Professor Kim Lee-Sup Lab’s Master’s Graduate Park Jun-Young Wins Best Paper Award at the International Design Automation Conference

 

<(From left to right) Professor Kim Lee-Sup, Master’s Graduate Park Jun-Young, Ph.D. Graduate Kang Myeong-Goo, Master’s Graduate Kim Yang-Gon, Ph.D. Graduate Shin Jae-Kang,    Ph.D. Candidate Han Yunki>

Professor Shinhyun Choi’s Research Team solves the Reliability Issues of Next-Generation Neuromorphic Computing

Neuromorphic computing, which implements AI computation in hardware by mimicking the human brain, has recently garnered significant attention. Memristors (conductance-changing devices), used as unit elements in neuromorphic computing, boast advantages such as low power consumption, high integration, and efficiency.

However, issues with irregular device characteristics have posed reliability problems for large-scale neuromorphic computing systems.

Our research team has developed a technology to enhance reliability, potentially accelerating the commercialization of neuromorphic computing.

 

On June 21, professor Shin-Hyun Choi’s research team announced a collaborative study with Hanyang University researchers. The study developed a doping method using aliovalent ions* to improve the reliability and performance of next-generation memory devices.

*Aliovalent ion: An ion with a different valence (a measure of its ability to bond) compared to the original atom.

 

The joint research team identified that doping with aliovalent ions could enhance the uniformity and performance of devices by addressing the primary issue of irregular device characteristic changes in next-generation memory devices, confirmed through experiments and atomic-level simulations.

 

Figure 1. Results of aliovalent ion doping developed in this study, demonstrating the improvement effects and the material principles underpinning them

 

The team reported that the appropriate injection of aliovalent halide ions into the oxide layer could solve the irregular device reliability problem, thereby improving device performance. This method was experimentally confirmed to enhance the uniformity, speed, and performance of device operation.

 

Furthermore, atomic-level simulation analysis showed that the performance improvement effect of the device was consistent with the experimental results observed in both crystalline and amorphous environments. The study revealed that doped aliovalent ions attract nearby oxygen vacancies, enabling stable device operation, and expand the space near the ions, allowing faster device operation.

 

Professor Shinhyun Choi states, “The aliovalent ion doping method we developed significantly enhances the reliability and performance of neuromorphic devices. This can contribute to the commercialization of next-generation memristor-based neuromorphic computing and can be applied to various semiconductor devices using the principles we uncovered.”

 

This research, with Master’s student Jongmin Bae and Postdoctoral researcher Choa Kwon from Hanyang University as co-first authors, was published in the June issue of the international journal ‘Science Advances’ (Paper title: Tunable ion energy barrier modulation through aliovalent halide doping for reliable and dynamic memristive neuromorphic systems).

 

The study was supported by the National Research Foundation of Korea’s Advanced Device Source Proprietary Technology Development Program, the Advanced Materials PIM Device Program, the Young Researcher Program, the Nano Convergence Technology Institute Semiconductor Process-based Nano-Medical Device Development Project, and the Innovation Support Program of the National Supercomputing Center.

Professor YongMan Ro’s research team develops a multimodal large language model that surpasses the performance of GPT-4V

 

On  June 20, 2024, Professor YongMan Ro’s research team announced that  they have developed and released an open-source multimodal large  language model that surpasses the visual performance of closed  commercial models like OpenAI’s ChatGPT/GPT-4V and Google’s Gemini-Pro. A  multimodal large language model refers to a massive language model  capable of processing not only text but also image data types.

 

The  recent advancement of large language models (LLMs) and the emergence of  visual instruction tuning have brought significant attention to  multimodal large language models. However, due to the support of  abundant computing resources by large overseas corporations, very large  models with parameters similar to the number of neural networks in the  human brain are being created.

These models are all developed in  private, leading to an ever-widening performance and technology gap  compared to large language models developed at the academic level. In  other words, the open-source large language models developed so far have  not only failed to match the performance of closed large language  models like ChatGPT/GPT-4V and Gemini-Pro, but also show a significant  performance gap.

 

To  improve the performance of multimodal large language models, existing  open-source large language models have either increased the model size  to enhance learning capacity or expanded the quality of visual  instruction tuning datasets that handle various vision language tasks.  However, these methods require vast computational resources or are  labor-intensive, highlighting the need for new efficient methods to  enhance the performance of multimodal large language models.

 

Professor YongMan Ro’s research team has announced the development of two technologies that significantly  enhance the visual performance of multimodal large language models  without significantly increasing the model size or creating high-quality  visual instruction tuning datasets.

 

The first technology developed by  the research team, CoLLaVO, verified that the primary reason existing  open-source multimodal large language models perform significantly lower  compared to closed models is due to a markedly lower capability in  object-level image understanding. Furthermore, they revealed that the  model’s object-level image understanding ability has a decisive and  significant correlation with its ability to handle visual-language  tasks.

 

To  efficiently enhance this capability and improve performance on  visual-language tasks, the team introduced a new visual prompt called  Crayon Prompt. This method leverages a computer vision model known as  panoptic segmentation to segment image information into background and  object units. Each segmented piece of information is then directly fed  into the multimodal large language model as input. 

 

Additionally, to  ensure that the information learned through the Crayon Prompt is not  lost during the visual instruction tuning phase, the team proposed an  innovative training strategy called Dual QLoRA.

This strategy trains  object-level image understanding ability and visual-language task  processing capability with different parameters, preventing the loss of  information between them.

Consequently, the CoLLaVO multimodal large  language model exhibits superior ability to distinguish between  background and objects within images, significantly enhancing its  one-dimensional visual discrimination ability.

 

 

< CoLLaVO Demo GIF >

 

[2] MoAI Demo GIF Video Clip https://github.com/ByungKwanLee/MoAI

< MoAI Demo GIF >

Professor Song Min Kim’s Research Team Wins Best Paper Award at ACM MobiSys 2024, an International Mobile Computing Conference

 

A research team led by Professor Song Min Kim from the Department of EE won the Best Paper Award at ACM MobiSys 2024, the top international conference in the field of mobile computing.

This achievement follows their previous Best Paper Award at ACM MobiSys 2022, making it even more significant as the two Ph.D students became the first in the world to win multiple Best Paper Awards at the three major conferences in mobile/wireless networks (MobiSys, MobiCom, SenSys) as the first authors.

 

Ph.D. candidates Kang Min Bae and Hankyeol Moon from the Department of Electrical and Electronic Engineering participated as co-first authors in Professor Kim’s research team.

They developed a technology using millimeter-wave backscatter to accurately locate targets obscured by obstacles with precision under 1 cm, earning them the Best Paper Award.

 

This research is expected to revolutionize the stability and accuracy of indoor positioning technology, leading to widespread adoption of location-based services in smart factories and augmented reality (AR), among other applications.

-Paper: https://doi.org/10.1145/3643832.3661857